The clocks for SPI busses were named wrongly which resulted in the
spi-mt65xx driver not requesting them. This has apparently been
worked around by marking the clocks required for SPI0 which is used
for SPI-NOR and SPI-NAND flash chips as critical.
Fix the device tree for all 3 generic SPI host controllers and no
longer mark clocks as critical.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Assign pwm function of PWM0 pin to the pwm-fan.
This is mostly just cosmetics as it basically reflects the default
setting of that pin.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add additionals possible pinctrl group for pwm2~7 on pins
pin 4 (GPIO_A) pwm7
pin 58 (JTAG_JTDI) pwm2
pin 59 (JTAG_JTDO) pwm3
pin 60 (JTAG_JTMS) pwm4
pin 61 (JTAG_JTCLK) pwm5
pin 62 (JTAG_JTRST_N) pwm6
They can be useful e.g. on the BPi-R4 as in that way pwm2~6 can be exposed
on the 26-pin header (pwm6 always, pwm2~5 instead of the full UART).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use pending patchset for 2.5GE PHY driver, unifying LED handling
accross all MediaTek Ethernet PHYs.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Backport newly introduced support for 'active-high' property and use
it to correctly implement polarity assignment for Aquantia PHY LEDs.
Previously the 'active-low' property was used to switch a LED PIN to
active-high ("drive VDD" in Aquantia-speak) mode.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
PMD Global Transmit Disable bit should be cleared for normal operation.
This should be HW default, however I found that on Asus RT-AX89X that uses
AQR113C PHY and firmware 5.4 this bit is set by default.
With this bit set the AQR cannot achieve a link with its link-partner and
it took me multiple hours of digging through the vendor GPL source to find
this out, so lets always clear this bit during .config_init() to avoid a
situation like this in the future.
aqr107_wait_processor_intensive_op() is moved up because datasheet notes
that any changes to this bit are processor intensive.
This is a modified version of patch that got merged upstream as AQR113C
has a separate config_init() upstream.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add memory regions and devices used for wireless offloading to the
device tree for MT7988.
This allows using WED on devices with MT7988 SoC and MT7995E, MT7996E or
MT7992E wireless controllers.
Devices with 4 GiB of RAM (or more) will still need ajustments to avoid
running out of swiotlb entries.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
commit eee3c695f3 ("linux-firmware: add offloading firmware for MT7988")
added mt7988_wo_{0,1}.bin in the 'mediatek/mt7988' directory while driver
currently expects the files in the 'mediatek' directory.
Import pending patch which changes the path in the driver header now
that the firmware has been added.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add INET diag socket monitoring interface module for MultiPath TCP.
It allows using native Linux socket diagnostic tools such as 'ss' for
Multipath TCP connections.
Co-authored-by: Rodrigo B. de Sousa Martins <rodrigo.sousa.577@gmail.com>
Signed-off-by: sKy King <29267720+sKyissKy@users.noreply.github.com>
Link: https://github.com/openwrt/openwrt/pull/12884
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Expose Kernel's CONFIG_MPTCP option and enable it by default for
!SMALL_FLASH targets.
The idea behind enabling it by default is to allow users of the binary
distribution to make use of MPTCP tunneling for link aggregation.
Using MPTCP for link aggregation is an often discussed topic in the
forum and there is even a whole OpenWrt fork (MPTCPRouter) just for that.
Enabling the kernel-side of the story by default will allow using MPTCP
on vanilla OpenWrt without having to build anything from source.
See also https://openwrt.org/docs/guide-user/network/mptcp
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
