* Adds the x86_64 dependency for mlxsw_core
* Removes the redundant mlxsw_core dependency
from mlxsw-minimal and mlxsw-spectrum
* Removes the DCB configuration symbols because
they were moved into the generic configuration
Signed-off-by: Til Kaiser <mail@tk154.de>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Set the boot flag for the igc, mlx4-core, and mlx5-core network device drivers
to load them at a more early stage of the boot process.
This is required for network drivers whose network interface PCI paths are set
via ucidef_set_network_device_path inside the 02_network script since it is
called after kernel modules are loaded from modules-boot.d but before they are
loaded from the modules.d directory.
Signed-off-by: Til Kaiser <mail@tk154.de>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The clocks for SPI busses were named wrongly which resulted in the
spi-mt65xx driver not requesting them. This has apparently been
worked around by marking the clocks required for SPI0 which is used
for SPI-NOR and SPI-NAND flash chips as critical.
Fix the device tree for all 3 generic SPI host controllers and no
longer mark clocks as critical.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Assign pwm function of PWM0 pin to the pwm-fan.
This is mostly just cosmetics as it basically reflects the default
setting of that pin.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add additionals possible pinctrl group for pwm2~7 on pins
pin 4 (GPIO_A) pwm7
pin 58 (JTAG_JTDI) pwm2
pin 59 (JTAG_JTDO) pwm3
pin 60 (JTAG_JTMS) pwm4
pin 61 (JTAG_JTCLK) pwm5
pin 62 (JTAG_JTRST_N) pwm6
They can be useful e.g. on the BPi-R4 as in that way pwm2~6 can be exposed
on the 26-pin header (pwm6 always, pwm2~5 instead of the full UART).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use pending patchset for 2.5GE PHY driver, unifying LED handling
accross all MediaTek Ethernet PHYs.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Backport newly introduced support for 'active-high' property and use
it to correctly implement polarity assignment for Aquantia PHY LEDs.
Previously the 'active-low' property was used to switch a LED PIN to
active-high ("drive VDD" in Aquantia-speak) mode.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
PMD Global Transmit Disable bit should be cleared for normal operation.
This should be HW default, however I found that on Asus RT-AX89X that uses
AQR113C PHY and firmware 5.4 this bit is set by default.
With this bit set the AQR cannot achieve a link with its link-partner and
it took me multiple hours of digging through the vendor GPL source to find
this out, so lets always clear this bit during .config_init() to avoid a
situation like this in the future.
aqr107_wait_processor_intensive_op() is moved up because datasheet notes
that any changes to this bit are processor intensive.
This is a modified version of patch that got merged upstream as AQR113C
has a separate config_init() upstream.
Signed-off-by: Robert Marko <robimarko@gmail.com>
