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ramips: mt7620: fix RGMII TXID PHY mode

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the register bits for TX delay and RX delay are opposites:
when TX delay bit is set, delay is enabled
when RX delay bit is set, delay is disabled

So, when both bits are unset, it is RX delay
and when both bits are set, it is TX delay

Note: TXID is the default RGMII mode of the SOC

Fixes: 5410a8e295 ("ramips: mt7620: add rgmii delays support")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 26c84b2e46)
This commit is contained in:
Michael Pratt 2021-05-01 14:17:11 -04:00 committed by Petr Štetiar
parent 6685eb29e5
commit 3f976d0225
1 changed files with 1 additions and 1 deletions
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2
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
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@ -196,7 +196,7 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
break;
case PHY_INTERFACE_MODE_RGMII_TXID:
mask = 0;
val_delay &= ~GSW_REG_GPCx_TXDELAY;
val_delay |= GSW_REG_GPCx_TXDELAY;
val_delay |= GSW_REG_GPCx_RXDELAY;
break;
case PHY_INTERFACE_MODE_MII: