mirror of
https://github.com/openwrt/targets.git
synced 2025-01-07 03:06:42 +08:00
ath25: import from openwrt/main
ath25 was dropped in the main repo, so lets add it here in case anyone needs it still. Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko
parent
a1497c4562
commit
5d2306e287
23
ath25/Makefile
Normal file
23
ath25/Makefile
Normal file
@ -0,0 +1,23 @@
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Copyright (C) 2006-2013 OpenWrt.org
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include $(TOPDIR)/rules.mk
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ARCH:=mips
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BOARD:=ath25
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BOARDNAME:=Atheros AR231x/AR5312
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FEATURES:=squashfs low_mem small_flash source-only
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SUBTARGETS:=generic
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KERNEL_PATCHVER:=5.15
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define Target/Description
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Build firmware images for Atheros SoC boards
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endef
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include $(INCLUDE_DIR)/target.mk
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DEFAULT_PACKAGES += wpad-basic-mbedtls kmod-ath5k swconfig kmod-gpio-button-hotplug
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$(eval $(call BuildTarget))
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12
ath25/base-files/etc/board.d/01_leds
Normal file
12
ath25/base-files/etc/board.d/01_leds
Normal file
@ -0,0 +1,12 @@
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# Copyright 2012-2015 OpenWrt.org
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#
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. /lib/functions/uci-defaults.sh
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board_config_update
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ucidef_set_led_netdev "wlan" "wlan" "wlan" "wlan0"
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board_config_flush
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exit 0
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27
ath25/base-files/etc/board.d/02_network
Normal file
27
ath25/base-files/etc/board.d/02_network
Normal file
@ -0,0 +1,27 @@
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. /lib/functions/uci-defaults.sh
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board_config_update
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if [ -e "/sys/bus/mdio_bus/drivers/IC+ IP175C/0:00" -o \
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-e "/sys/bus/mdio_bus/drivers/IC+ IP17xx/0:00" ] && \
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[ -x /sbin/swconfig ];
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then
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ucidef_add_switch "eth0" \
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"0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "5@eth0"
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elif [ -e "/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00" -o \
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-e "/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10" ];
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then
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ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2"
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elif [ -d /sys/class/net/eth1 ]; then
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ucidef_set_interfaces_lan_wan "eth0" "eth1"
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else
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ucidef_set_interface_lan "eth0"
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fi
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board_config_flush
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exit 0
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29
ath25/base-files/lib/preinit/15_preinit_iface_atheros
Normal file
29
ath25/base-files/lib/preinit/15_preinit_iface_atheros
Normal file
@ -0,0 +1,29 @@
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preinit_ip() {
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if [ -z "$pi_ifname" ]; then
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grep -q 'Atheros AR231[567]' /proc/cpuinfo && {
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if [ -e "/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00" -o \
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-e "/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10" ]; then
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ip link set eth0 up
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ip link add link eth0 name eth0.1 type vlan id 1
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ifname=eth0.1
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else
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ifname=eth0
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fi
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pi_ifname=$ifname
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}
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fi
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[ -n "$pi_ifname" ] && grep -q "$pi_ifname" /proc/net/dev && {
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ip addr add $pi_ip/$pi_netmask broadcast $pi_broadcast dev $pi_ifname
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ip link set $pi_ifname up
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}
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}
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preinit_ip_deconfig() {
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if [ -e "/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00" -o \
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-e "/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10" ]; then
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ip link del eth0.1 2>/dev/null
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ip link set $pi_ifname down
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elif [ -n "$pi_ifname" ]; then
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ip -4 addr flush dev $pi_ifname
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fi
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}
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76
ath25/base-files/lib/upgrade/platform.sh
Normal file
76
ath25/base-files/lib/upgrade/platform.sh
Normal file
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CI_BLKSZ=65536
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CI_LDADR=0x80041000
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platform_find_partitions() {
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local first dev size erasesize name
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while read dev size erasesize name; do
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name=${name#'"'}; name=${name%'"'}
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case "$name" in
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vmlinux.bin.l7|kernel|linux|rootfs)
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if [ -z "$first" ]; then
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first="$name"
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else
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echo "$erasesize:$first:$name"
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break
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fi
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;;
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esac
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done < /proc/mtd
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}
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platform_find_kernelpart() {
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local part
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for part in "${1%:*}" "${1#*:}"; do
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case "$part" in
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vmlinux.bin.l7|kernel|linux)
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echo "$part"
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break
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;;
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esac
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done
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}
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platform_check_image() {
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[ "$#" -gt 1 ] && return 1
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case "$(get_magic_word "$1")" in
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# Combined Image
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4349)
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local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null)
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local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}"
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if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then
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return 0
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else
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echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)"
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return 1
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fi
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;;
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*)
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echo "Invalid image. Use combined .img files on this platform"
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return 1
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;;
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esac
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}
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platform_do_upgrade() {
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local partitions=$(platform_find_partitions)
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local kernelpart=$(platform_find_kernelpart "${partitions#*:}")
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local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}"
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local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null)
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local kern_blocks=$(($kern_length / $CI_BLKSZ))
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local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ))
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if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \
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[ ${kern_blocks:-0} -gt 0 ] && \
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[ ${root_blocks:-0} -gt ${kern_blocks:-0} ] && \
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[ ${erase_size:-0} -gt 0 ];
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then
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local append=""
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[ -f "$UPGRADE_BACKUP" ] && append="-j $UPGRADE_BACKUP"
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( dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null; \
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dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null ) | \
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mtd -r $append -F$kernelpart:$kern_length:$CI_LDADR,rootfs write - $partitions
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fi
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}
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132
ath25/config-5.15
Normal file
132
ath25/config-5.15
Normal file
@ -0,0 +1,132 @@
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CONFIG_ADM6996_PHY=y
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CONFIG_AR2315_WDT=y
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CONFIG_AR8216_PHY=y
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CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MMAP_RND_BITS_MAX=15
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ATH25=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_CEVT_R4K=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2"
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CONFIG_CMDLINE_BOOL=y
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# CONFIG_CMDLINE_OVERRIDE is not set
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# CONFIG_COMMON_CLK is not set
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CPU_GENERIC_DUMP_TLB=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_MIPS32=y
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CONFIG_CPU_MIPS32_R1=y
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CONFIG_CPU_MIPSR1=y
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CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
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CONFIG_CPU_R4K_CACHE_TLB=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CSRC_R4K=y
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CONFIG_DMA_NONCOHERENT=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_ETHERNET_PACKET_MANGLE=y
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CONFIG_FORCE_PCI=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_FIND_FIRST_BIT=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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CONFIG_GENERIC_IOMAP=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_LIB_ASHLDI3=y
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CONFIG_GENERIC_LIB_ASHRDI3=y
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CONFIG_GENERIC_LIB_CMPDI2=y
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CONFIG_GENERIC_LIB_LSHRDI3=y
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CONFIG_GENERIC_LIB_UCMPDI2=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GPIO_AR2315=y
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CONFIG_GPIO_AR5312=y
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CONFIG_GPIO_CDEV=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HW_RANDOM=y
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CONFIG_HZ_PERIODIC=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IP17XX_PHY=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_MIPS_CPU=y
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CONFIG_IRQ_WORK=y
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CONFIG_LEDS_GPIO=y
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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CONFIG_MEMFD_CREATE=y
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CONFIG_MIGRATION=y
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CONFIG_MIPS=y
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CONFIG_MIPS_ASID_BITS=8
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CONFIG_MIPS_ASID_SHIFT=0
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CONFIG_MIPS_CLOCK_VSYSCALL=y
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# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
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CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
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CONFIG_MIPS_EBPF_JIT=y
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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CONFIG_MIPS_LD_CAN_LINK_VDSO=y
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MTD_AR2315=y
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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# CONFIG_MTD_CFI_GEOMETRY is not set
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_MYLOADER_PARTS=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
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CONFIG_MTD_REDBOOT_PARTS=y
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CONFIG_MVSWITCH_PHY=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NET_AR231X=y
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CONFIG_NET_SELFTESTS=y
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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# CONFIG_OF is not set
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CONFIG_PCI=y
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CONFIG_PCI_AR2315=y
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CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_DRIVERS_LEGACY=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PGTABLE_LEVELS=2
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CONFIG_PHYLIB=y
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CONFIG_PTP_1588_CLOCK_OPTIONAL=y
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CONFIG_SERIAL_8250_NR_UARTS=1
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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CONFIG_SERIAL_MCTRL_GPIO=y
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CONFIG_SOC_AR2315=y
|
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CONFIG_SOC_AR5312=y
|
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CONFIG_SRCU=y
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# CONFIG_SWAP is not set
|
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CONFIG_SWCONFIG=y
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CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
|
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
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CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
|
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CONFIG_TARGET_ISA_REV=1
|
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CONFIG_TICK_CPU_ACCOUNTING=y
|
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CONFIG_TINY_SRCU=y
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CONFIG_USB_SUPPORT=y
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454
ath25/files/drivers/net/phy/mvswitch.c
Normal file
454
ath25/files/drivers/net/phy/mvswitch.c
Normal file
@ -0,0 +1,454 @@
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/*
|
||||
* Marvell 88E6060 switch driver
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||||
* Copyright (c) 2008 Felix Fietkau <nbd@nbd.name>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License v2 as published by the
|
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* Free Software Foundation
|
||||
*/
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#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
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#include <linux/skbuff.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include "mvswitch.h"
|
||||
|
||||
/* Undefine this to use trailer mode instead.
|
||||
* I don't know if header mode works with all chips */
|
||||
#define HEADER_MODE 1
|
||||
|
||||
MODULE_DESCRIPTION("Marvell 88E6060 Switch driver");
|
||||
MODULE_AUTHOR("Felix Fietkau");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
#define MVSWITCH_MAGIC 0x88E6060
|
||||
|
||||
struct mvswitch_priv {
|
||||
netdev_features_t orig_features;
|
||||
u8 vlans[16];
|
||||
};
|
||||
|
||||
#define to_mvsw(_phy) ((struct mvswitch_priv *) (_phy)->priv)
|
||||
|
||||
static inline u16
|
||||
r16(struct phy_device *phydev, int addr, int reg)
|
||||
{
|
||||
struct mii_bus *bus = phydev->mdio.bus;
|
||||
|
||||
return bus->read(bus, addr, reg);
|
||||
}
|
||||
|
||||
static inline void
|
||||
w16(struct phy_device *phydev, int addr, int reg, u16 val)
|
||||
{
|
||||
struct mii_bus *bus = phydev->mdio.bus;
|
||||
|
||||
bus->write(bus, addr, reg, val);
|
||||
}
|
||||
|
||||
|
||||
static struct sk_buff *
|
||||
mvswitch_mangle_tx(struct net_device *dev, struct sk_buff *skb)
|
||||
{
|
||||
struct mvswitch_priv *priv;
|
||||
char *buf = NULL;
|
||||
u16 vid;
|
||||
|
||||
priv = dev->phy_ptr;
|
||||
if (unlikely(!priv))
|
||||
goto error;
|
||||
|
||||
if (unlikely(skb->len < 16))
|
||||
goto error;
|
||||
|
||||
#ifdef HEADER_MODE
|
||||
if (__vlan_hwaccel_get_tag(skb, &vid))
|
||||
goto error;
|
||||
|
||||
if (skb_cloned(skb) || (skb->len <= 62) || (skb_headroom(skb) < MV_HEADER_SIZE)) {
|
||||
if (pskb_expand_head(skb, MV_HEADER_SIZE, (skb->len < 62 ? 62 - skb->len : 0), GFP_ATOMIC))
|
||||
goto error_expand;
|
||||
if (skb->len < 62)
|
||||
skb->len = 62;
|
||||
}
|
||||
buf = skb_push(skb, MV_HEADER_SIZE);
|
||||
#else
|
||||
if (__vlan_get_tag(skb, &vid))
|
||||
goto error;
|
||||
|
||||
if (unlikely((vid > 15 || !priv->vlans[vid])))
|
||||
goto error;
|
||||
|
||||
if (skb->len <= 64) {
|
||||
if (pskb_expand_head(skb, 0, 64 + MV_TRAILER_SIZE - skb->len, GFP_ATOMIC))
|
||||
goto error_expand;
|
||||
|
||||
buf = skb->data + 64;
|
||||
skb->len = 64 + MV_TRAILER_SIZE;
|
||||
} else {
|
||||
if (skb_cloned(skb) || unlikely(skb_tailroom(skb) < 4)) {
|
||||
if (pskb_expand_head(skb, 0, 4, GFP_ATOMIC))
|
||||
goto error_expand;
|
||||
}
|
||||
buf = skb_put(skb, 4);
|
||||
}
|
||||
|
||||
/* move the ethernet header 4 bytes forward, overwriting the vlan tag */
|
||||
memmove(skb->data + 4, skb->data, 12);
|
||||
skb->data += 4;
|
||||
skb->len -= 4;
|
||||
skb->mac_header += 4;
|
||||
#endif
|
||||
|
||||
if (!buf)
|
||||
goto error;
|
||||
|
||||
|
||||
#ifdef HEADER_MODE
|
||||
/* prepend the tag */
|
||||
*((__be16 *) buf) = cpu_to_be16(
|
||||
((vid << MV_HEADER_VLAN_S) & MV_HEADER_VLAN_M) |
|
||||
((priv->vlans[vid] << MV_HEADER_PORTS_S) & MV_HEADER_PORTS_M)
|
||||
);
|
||||
#else
|
||||
/* append the tag */
|
||||
*((__be32 *) buf) = cpu_to_be32((
|
||||
(MV_TRAILER_OVERRIDE << MV_TRAILER_FLAGS_S) |
|
||||
((priv->vlans[vid] & MV_TRAILER_PORTS_M) << MV_TRAILER_PORTS_S)
|
||||
));
|
||||
#endif
|
||||
|
||||
return skb;
|
||||
|
||||
error_expand:
|
||||
if (net_ratelimit())
|
||||
printk("%s: failed to expand/update skb for the switch\n", dev->name);
|
||||
|
||||
error:
|
||||
/* any errors? drop the packet! */
|
||||
dev_kfree_skb_any(skb);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void
|
||||
mvswitch_mangle_rx(struct net_device *dev, struct sk_buff *skb)
|
||||
{
|
||||
struct mvswitch_priv *priv;
|
||||
unsigned char *buf;
|
||||
int vlan = -1;
|
||||
int i;
|
||||
|
||||
priv = dev->phy_ptr;
|
||||
if (WARN_ON_ONCE(!priv))
|
||||
return;
|
||||
|
||||
#ifdef HEADER_MODE
|
||||
buf = skb->data;
|
||||
skb_pull(skb, MV_HEADER_SIZE);
|
||||
#else
|
||||
buf = skb->data + skb->len - MV_TRAILER_SIZE;
|
||||
if (buf[0] != 0x80)
|
||||
return;
|
||||
#endif
|
||||
|
||||
/* look for the vlan matching the incoming port */
|
||||
for (i = 0; i < ARRAY_SIZE(priv->vlans); i++) {
|
||||
if ((1 << buf[1]) & priv->vlans[i])
|
||||
vlan = i;
|
||||
}
|
||||
|
||||
if (vlan == -1)
|
||||
return;
|
||||
|
||||
__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
mvswitch_wait_mask(struct phy_device *pdev, int addr, int reg, u16 mask, u16 val)
|
||||
{
|
||||
int i = 100;
|
||||
u16 r;
|
||||
|
||||
do {
|
||||
r = r16(pdev, addr, reg) & mask;
|
||||
if (r == val)
|
||||
return 0;
|
||||
} while(--i > 0);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int
|
||||
mvswitch_config_init(struct phy_device *pdev)
|
||||
{
|
||||
struct mvswitch_priv *priv = to_mvsw(pdev);
|
||||
struct net_device *dev = pdev->attached_dev;
|
||||
u8 vlmap = 0;
|
||||
int i;
|
||||
|
||||
if (!dev)
|
||||
return -EINVAL;
|
||||
|
||||
printk("%s: Marvell 88E6060 PHY driver attached.\n", dev->name);
|
||||
linkmode_zero(pdev->supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pdev->supported);
|
||||
linkmode_copy(pdev->advertising, pdev->supported);
|
||||
dev->phy_ptr = priv;
|
||||
pdev->irq = PHY_POLL;
|
||||
#ifdef HEADER_MODE
|
||||
dev->flags |= IFF_PROMISC;
|
||||
#endif
|
||||
|
||||
/* initialize default vlans */
|
||||
for (i = 0; i < MV_PORTS; i++)
|
||||
priv->vlans[(i == MV_WANPORT ? 2 : 1)] |= (1 << i);
|
||||
|
||||
/* before entering reset, disable all ports */
|
||||
for (i = 0; i < MV_PORTS; i++)
|
||||
w16(pdev, MV_PORTREG(CONTROL, i), 0x00);
|
||||
|
||||
msleep(2); /* wait for the status change to settle in */
|
||||
|
||||
/* put the ATU in reset */
|
||||
w16(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET);
|
||||
|
||||
i = mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET, 0);
|
||||
if (i < 0) {
|
||||
printk("%s: Timeout waiting for the switch to reset.\n", dev->name);
|
||||
return i;
|
||||
}
|
||||
|
||||
/* set the ATU flags */
|
||||
w16(pdev, MV_SWITCHREG(ATU_CTRL),
|
||||
MV_ATUCTL_NO_LEARN |
|
||||
MV_ATUCTL_ATU_1K |
|
||||
MV_ATUCTL_AGETIME(MV_ATUCTL_AGETIME_MIN) /* minimum without disabling ageing */
|
||||
);
|
||||
|
||||
/* initialize the cpu port */
|
||||
w16(pdev, MV_PORTREG(CONTROL, MV_CPUPORT),
|
||||
#ifdef HEADER_MODE
|
||||
MV_PORTCTRL_HEADER |
|
||||
#else
|
||||
MV_PORTCTRL_RXTR |
|
||||
MV_PORTCTRL_TXTR |
|
||||
#endif
|
||||
MV_PORTCTRL_ENABLED
|
||||
);
|
||||
/* wait for the phy change to settle in */
|
||||
msleep(2);
|
||||
for (i = 0; i < MV_PORTS; i++) {
|
||||
u8 pvid = 0;
|
||||
int j;
|
||||
|
||||
vlmap = 0;
|
||||
|
||||
/* look for the matching vlan */
|
||||
for (j = 0; j < ARRAY_SIZE(priv->vlans); j++) {
|
||||
if (priv->vlans[j] & (1 << i)) {
|
||||
vlmap = priv->vlans[j];
|
||||
pvid = j;
|
||||
}
|
||||
}
|
||||
/* leave port unconfigured if it's not part of a vlan */
|
||||
if (!vlmap)
|
||||
continue;
|
||||
|
||||
/* add the cpu port to the allowed destinations list */
|
||||
vlmap |= (1 << MV_CPUPORT);
|
||||
|
||||
/* take port out of its own vlan destination map */
|
||||
vlmap &= ~(1 << i);
|
||||
|
||||
/* apply vlan settings */
|
||||
w16(pdev, MV_PORTREG(VLANMAP, i),
|
||||
MV_PORTVLAN_PORTS(vlmap) |
|
||||
MV_PORTVLAN_ID(i)
|
||||
);
|
||||
|
||||
/* re-enable port */
|
||||
w16(pdev, MV_PORTREG(CONTROL, i),
|
||||
MV_PORTCTRL_ENABLED
|
||||
);
|
||||
}
|
||||
|
||||
w16(pdev, MV_PORTREG(VLANMAP, MV_CPUPORT),
|
||||
MV_PORTVLAN_ID(MV_CPUPORT)
|
||||
);
|
||||
|
||||
/* set the port association vector */
|
||||
for (i = 0; i <= MV_PORTS; i++) {
|
||||
w16(pdev, MV_PORTREG(ASSOC, i),
|
||||
MV_PORTASSOC_PORTS(1 << i)
|
||||
);
|
||||
}
|
||||
|
||||
/* init switch control */
|
||||
w16(pdev, MV_SWITCHREG(CTRL),
|
||||
MV_SWITCHCTL_MSIZE |
|
||||
MV_SWITCHCTL_DROP
|
||||
);
|
||||
|
||||
dev->eth_mangle_rx = mvswitch_mangle_rx;
|
||||
dev->eth_mangle_tx = mvswitch_mangle_tx;
|
||||
priv->orig_features = dev->features;
|
||||
|
||||
#ifdef HEADER_MODE
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)
|
||||
dev->priv_flags |= IFF_NO_IP_ALIGN;
|
||||
#else
|
||||
dev->extra_priv_flags |= IFF_NO_IP_ALIGN;
|
||||
#endif
|
||||
dev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
|
||||
#else
|
||||
dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mvswitch_read_status(struct phy_device *pdev)
|
||||
{
|
||||
pdev->speed = SPEED_100;
|
||||
pdev->duplex = DUPLEX_FULL;
|
||||
pdev->link = 1;
|
||||
|
||||
/* XXX ugly workaround: we can't force the switch
|
||||
* to gracefully handle hosts moving from one port to another,
|
||||
* so we have to regularly clear the ATU database */
|
||||
|
||||
/* wait for the ATU to become available */
|
||||
mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0);
|
||||
|
||||
/* flush the ATU */
|
||||
w16(pdev, MV_SWITCHREG(ATU_OP),
|
||||
MV_ATUOP_INPROGRESS |
|
||||
MV_ATUOP_FLUSH_ALL
|
||||
);
|
||||
|
||||
/* wait for operation to complete */
|
||||
mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mvswitch_aneg_done(struct phy_device *phydev)
|
||||
{
|
||||
return 1; /* Return any positive value */
|
||||
}
|
||||
|
||||
static int
|
||||
mvswitch_config_aneg(struct phy_device *phydev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
mvswitch_detach(struct phy_device *pdev)
|
||||
{
|
||||
struct mvswitch_priv *priv = to_mvsw(pdev);
|
||||
struct net_device *dev = pdev->attached_dev;
|
||||
|
||||
if (!dev)
|
||||
return;
|
||||
|
||||
dev->phy_ptr = NULL;
|
||||
dev->eth_mangle_rx = NULL;
|
||||
dev->eth_mangle_tx = NULL;
|
||||
dev->features = priv->orig_features;
|
||||
#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)
|
||||
dev->priv_flags &= ~IFF_NO_IP_ALIGN;
|
||||
#else
|
||||
dev->extra_priv_flags &= ~IFF_NO_IP_ALIGN;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
mvswitch_remove(struct phy_device *pdev)
|
||||
{
|
||||
struct mvswitch_priv *priv = to_mvsw(pdev);
|
||||
|
||||
kfree(priv);
|
||||
}
|
||||
|
||||
static int
|
||||
mvswitch_probe(struct phy_device *pdev)
|
||||
{
|
||||
struct mvswitch_priv *priv;
|
||||
|
||||
priv = kzalloc(sizeof(struct mvswitch_priv), GFP_KERNEL);
|
||||
if (priv == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
pdev->priv = priv;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mvswitch_fixup(struct phy_device *dev)
|
||||
{
|
||||
struct mii_bus *bus = dev->mdio.bus;
|
||||
u16 reg;
|
||||
|
||||
if (dev->mdio.addr != 0x10)
|
||||
return 0;
|
||||
|
||||
reg = bus->read(bus, MV_PORTREG(IDENT, 0)) & MV_IDENT_MASK;
|
||||
if (reg != MV_IDENT_VALUE)
|
||||
return 0;
|
||||
|
||||
dev->phy_id = MVSWITCH_MAGIC;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static struct phy_driver mvswitch_driver = {
|
||||
.name = "Marvell 88E6060",
|
||||
.phy_id = MVSWITCH_MAGIC,
|
||||
.phy_id_mask = 0xffffffff,
|
||||
.features = PHY_BASIC_FEATURES,
|
||||
.probe = &mvswitch_probe,
|
||||
.remove = &mvswitch_remove,
|
||||
.detach = &mvswitch_detach,
|
||||
.config_init = &mvswitch_config_init,
|
||||
.config_aneg = &mvswitch_config_aneg,
|
||||
.aneg_done = &mvswitch_aneg_done,
|
||||
.read_status = &mvswitch_read_status,
|
||||
};
|
||||
|
||||
static int __init
|
||||
mvswitch_init(void)
|
||||
{
|
||||
phy_register_fixup_for_id(PHY_ANY_ID, mvswitch_fixup);
|
||||
return phy_driver_register(&mvswitch_driver, THIS_MODULE);
|
||||
}
|
||||
|
||||
static void __exit
|
||||
mvswitch_exit(void)
|
||||
{
|
||||
phy_driver_unregister(&mvswitch_driver);
|
||||
}
|
||||
|
||||
module_init(mvswitch_init);
|
||||
module_exit(mvswitch_exit);
|
||||
145
ath25/files/drivers/net/phy/mvswitch.h
Normal file
145
ath25/files/drivers/net/phy/mvswitch.h
Normal file
@ -0,0 +1,145 @@
|
||||
/*
|
||||
* Marvell 88E6060 switch driver
|
||||
* Copyright (c) 2008 Felix Fietkau <nbd@nbd.name>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License v2 as published by the
|
||||
* Free Software Foundation
|
||||
*/
|
||||
#ifndef __MVSWITCH_H
|
||||
#define __MVSWITCH_H
|
||||
|
||||
#define MV_HEADER_SIZE 2
|
||||
#define MV_HEADER_PORTS_M 0x001f
|
||||
#define MV_HEADER_PORTS_S 0
|
||||
#define MV_HEADER_VLAN_M 0xf000
|
||||
#define MV_HEADER_VLAN_S 12
|
||||
|
||||
#define MV_TRAILER_SIZE 4
|
||||
#define MV_TRAILER_PORTS_M 0x1f
|
||||
#define MV_TRAILER_PORTS_S 16
|
||||
#define MV_TRAILER_FLAGS_S 24
|
||||
#define MV_TRAILER_OVERRIDE 0x80
|
||||
|
||||
|
||||
#define MV_PORTS 5
|
||||
#define MV_WANPORT 4
|
||||
#define MV_CPUPORT 5
|
||||
|
||||
#define MV_BASE 0x10
|
||||
|
||||
#define MV_PHYPORT_BASE (MV_BASE + 0x0)
|
||||
#define MV_PHYPORT(_n) (MV_PHYPORT_BASE + (_n))
|
||||
#define MV_SWITCHPORT_BASE (MV_BASE + 0x8)
|
||||
#define MV_SWITCHPORT(_n) (MV_SWITCHPORT_BASE + (_n))
|
||||
#define MV_SWITCHREGS (MV_BASE + 0xf)
|
||||
|
||||
enum {
|
||||
MV_PHY_CONTROL = 0x00,
|
||||
MV_PHY_STATUS = 0x01,
|
||||
MV_PHY_IDENT0 = 0x02,
|
||||
MV_PHY_IDENT1 = 0x03,
|
||||
MV_PHY_ANEG = 0x04,
|
||||
MV_PHY_LINK_ABILITY = 0x05,
|
||||
MV_PHY_ANEG_EXPAND = 0x06,
|
||||
MV_PHY_XMIT_NEXTP = 0x07,
|
||||
MV_PHY_LINK_NEXTP = 0x08,
|
||||
MV_PHY_CONTROL1 = 0x10,
|
||||
MV_PHY_STATUS1 = 0x11,
|
||||
MV_PHY_INTR_EN = 0x12,
|
||||
MV_PHY_INTR_STATUS = 0x13,
|
||||
MV_PHY_INTR_PORT = 0x14,
|
||||
MV_PHY_RECV_COUNTER = 0x16,
|
||||
MV_PHY_LED_PARALLEL = 0x16,
|
||||
MV_PHY_LED_STREAM = 0x17,
|
||||
MV_PHY_LED_CTRL = 0x18,
|
||||
MV_PHY_LED_OVERRIDE = 0x19,
|
||||
MV_PHY_VCT_CTRL = 0x1a,
|
||||
MV_PHY_VCT_STATUS = 0x1b,
|
||||
MV_PHY_CONTROL2 = 0x1e
|
||||
};
|
||||
#define MV_PHYREG(_type, _port) MV_PHYPORT(_port), MV_PHY_##_type
|
||||
|
||||
enum {
|
||||
MV_PORT_STATUS = 0x00,
|
||||
MV_PORT_IDENT = 0x03,
|
||||
MV_PORT_CONTROL = 0x04,
|
||||
MV_PORT_VLANMAP = 0x06,
|
||||
MV_PORT_ASSOC = 0x0b,
|
||||
MV_PORT_RXCOUNT = 0x10,
|
||||
MV_PORT_TXCOUNT = 0x11,
|
||||
};
|
||||
#define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type
|
||||
|
||||
enum {
|
||||
MV_PORTCTRL_BLOCK = (1 << 0),
|
||||
MV_PORTCTRL_LEARN = (2 << 0),
|
||||
MV_PORTCTRL_ENABLED = (3 << 0),
|
||||
MV_PORTCTRL_VLANTUN = (1 << 7), /* Enforce VLANs on packets */
|
||||
MV_PORTCTRL_RXTR = (1 << 8), /* Enable Marvell packet trailer for ingress */
|
||||
MV_PORTCTRL_HEADER = (1 << 11), /* Enable Marvell packet header mode for port */
|
||||
MV_PORTCTRL_TXTR = (1 << 14), /* Enable Marvell packet trailer for egress */
|
||||
MV_PORTCTRL_FORCEFL = (1 << 15), /* force flow control */
|
||||
};
|
||||
|
||||
#define MV_PORTVLAN_ID(_n) (((_n) & 0xf) << 12)
|
||||
#define MV_PORTVLAN_PORTS(_n) ((_n) & 0x3f)
|
||||
|
||||
#define MV_PORTASSOC_PORTS(_n) ((_n) & 0x1f)
|
||||
#define MV_PORTASSOC_MONITOR (1 << 15)
|
||||
|
||||
enum {
|
||||
MV_SWITCH_MAC0 = 0x01,
|
||||
MV_SWITCH_MAC1 = 0x02,
|
||||
MV_SWITCH_MAC2 = 0x03,
|
||||
MV_SWITCH_CTRL = 0x04,
|
||||
MV_SWITCH_ATU_CTRL = 0x0a,
|
||||
MV_SWITCH_ATU_OP = 0x0b,
|
||||
MV_SWITCH_ATU_DATA = 0x0c,
|
||||
MV_SWITCH_ATU_MAC0 = 0x0d,
|
||||
MV_SWITCH_ATU_MAC1 = 0x0e,
|
||||
MV_SWITCH_ATU_MAC2 = 0x0f,
|
||||
};
|
||||
#define MV_SWITCHREG(_type) MV_SWITCHREGS, MV_SWITCH_##_type
|
||||
|
||||
enum {
|
||||
MV_SWITCHCTL_EEIE = (1 << 0), /* EEPROM interrupt enable */
|
||||
MV_SWITCHCTL_PHYIE = (1 << 1), /* PHY interrupt enable */
|
||||
MV_SWITCHCTL_ATUDONE= (1 << 2), /* ATU done interrupt enable */
|
||||
MV_SWITCHCTL_ATUIE = (1 << 3), /* ATU interrupt enable */
|
||||
MV_SWITCHCTL_CTRMODE= (1 << 8), /* statistics for rx and tx errors */
|
||||
MV_SWITCHCTL_RELOAD = (1 << 9), /* reload registers from eeprom */
|
||||
MV_SWITCHCTL_MSIZE = (1 << 10), /* increase maximum frame size */
|
||||
MV_SWITCHCTL_DROP = (1 << 13), /* discard frames with excessive collisions */
|
||||
};
|
||||
|
||||
enum {
|
||||
#define MV_ATUCTL_AGETIME_MIN 16
|
||||
#define MV_ATUCTL_AGETIME_MAX 4080
|
||||
#define MV_ATUCTL_AGETIME(_n) ((((_n) / 16) & 0xff) << 4)
|
||||
MV_ATUCTL_ATU_256 = (0 << 12),
|
||||
MV_ATUCTL_ATU_512 = (1 << 12),
|
||||
MV_ATUCTL_ATU_1K = (2 << 12),
|
||||
MV_ATUCTL_ATUMASK = (3 << 12),
|
||||
MV_ATUCTL_NO_LEARN = (1 << 14),
|
||||
MV_ATUCTL_RESET = (1 << 15),
|
||||
};
|
||||
|
||||
enum {
|
||||
#define MV_ATUOP_DBNUM(_n) ((_n) & 0x0f)
|
||||
|
||||
MV_ATUOP_NOOP = (0 << 12),
|
||||
MV_ATUOP_FLUSH_ALL = (1 << 12),
|
||||
MV_ATUOP_FLUSH_U = (2 << 12),
|
||||
MV_ATUOP_LOAD_DB = (3 << 12),
|
||||
MV_ATUOP_GET_NEXT = (4 << 12),
|
||||
MV_ATUOP_FLUSH_DB = (5 << 12),
|
||||
MV_ATUOP_FLUSH_DB_UU= (6 << 12),
|
||||
|
||||
MV_ATUOP_INPROGRESS = (1 << 15),
|
||||
};
|
||||
|
||||
#define MV_IDENT_MASK 0xfff0
|
||||
#define MV_IDENT_VALUE 0x0600
|
||||
|
||||
#endif
|
||||
1
ath25/generic/target.mk
Normal file
1
ath25/generic/target.mk
Normal file
@ -0,0 +1 @@
|
||||
BOARDNAME:=Generic
|
||||
118
ath25/image/Makefile
Normal file
118
ath25/image/Makefile
Normal file
@ -0,0 +1,118 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Copyright (C) 2006-2010 OpenWrt.org
|
||||
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
define Build/mkfwimage
|
||||
$(STAGING_DIR_HOST)/bin/mkfwimage \
|
||||
-B $(1).$(VERSION_DIST).$(REVISION) \
|
||||
-k $(IMAGE_KERNEL) \
|
||||
-r $(IMAGE_ROOTFS) \
|
||||
-o $@.new && \
|
||||
mv $@.new $@
|
||||
endef
|
||||
|
||||
define Build/combined-image
|
||||
-sh $(TOPDIR)/scripts/combined-image.sh \
|
||||
"$(IMAGE_KERNEL)" \
|
||||
"$(IMAGE_ROOTFS)" \
|
||||
"$@.new" && \
|
||||
mv $@.new $@
|
||||
endef
|
||||
|
||||
define Build/mkmylofw
|
||||
$(STAGING_DIR_HOST)/bin/mkmylofw -B $(1) \
|
||||
-p0x020000:0x130000:ah:0x80041000:linux:$(IMAGE_KERNEL) \
|
||||
-p0x150000:0x2a0000:::rootfs:$(IMAGE_ROOTFS) \
|
||||
$@.new && \
|
||||
mv $@.new $@
|
||||
endef
|
||||
|
||||
define Build/gzip-kernel
|
||||
gzip -9n -c $@ > $@.gz
|
||||
dd if=$@.gz of=$@ bs=65536 conv=sync
|
||||
endef
|
||||
|
||||
define Build/lzma-kernel
|
||||
$(STAGING_DIR_HOST)/bin/lzma e $@ $@.l7
|
||||
dd if=$@.l7 of=$@ bs=65536 conv=sync
|
||||
endef
|
||||
|
||||
define Build/copy-kernel
|
||||
rm -f $@ $@.elf
|
||||
cp $< $@
|
||||
cp $<.elf $@.elf
|
||||
endef
|
||||
|
||||
define Build/elf-kernel
|
||||
cp $(IMAGE_KERNEL).elf $@
|
||||
endef
|
||||
|
||||
|
||||
define Device/Default
|
||||
PROFILES = Default $$(DEVICE_NAME)
|
||||
KERNEL := copy-kernel | lzma-kernel
|
||||
KERNEL_INITRAMFS = kernel-bin
|
||||
KERNEL_INITRAMFS_NAME := vmlinux-initramfs.elf
|
||||
KERNEL_INITRAMFS_SUFFIX := -kernel.elf
|
||||
IMAGES := sysupgrade.bin
|
||||
FILESYSTEMS := squashfs
|
||||
endef
|
||||
|
||||
define Device/generic
|
||||
DEVICE_VENDOR := Atheros
|
||||
DEVICE_MODEL := Generic AR2xxx board
|
||||
IMAGES := kernel.lzma kernel.elf kernel.gz rootfs.bin sysupgrade.bin
|
||||
IMAGE/kernel.gz := elf-kernel | gzip-kernel
|
||||
IMAGE/kernel.elf := elf-kernel
|
||||
IMAGE/kernel.lzma := elf-kernel | lzma-kernel
|
||||
IMAGE/rootfs.bin := append-rootfs | pad-rootfs | pad-to 128k
|
||||
IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | combined-image
|
||||
DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(if $$(findstring kernel,$$(2)),,$$(1)-)$$(2)
|
||||
endef
|
||||
TARGET_DEVICES += generic
|
||||
|
||||
define Device/ubnt_picostation-2
|
||||
DEVICE_VENDOR := Ubiquiti
|
||||
DEVICE_MODEL := Picostation 2 (XS2-8)
|
||||
IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkfwimage XS2-8 -v XS2.ar2316
|
||||
endef
|
||||
TARGET_DEVICES += ubnt_picostation-2
|
||||
|
||||
define Device/ubnt_nanostation-2
|
||||
DEVICE_VENDOR := Ubiquiti
|
||||
DEVICE_MODEL := Nanostation 2 (XS2)
|
||||
IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkfwimage XS2 -v XS2.ar2316
|
||||
DEFAULT := n
|
||||
endef
|
||||
TARGET_DEVICES += ubnt_nanostation-2
|
||||
|
||||
define Device/ubnt_nanostation-5
|
||||
DEVICE_VENDOR := Ubiquiti
|
||||
DEVICE_MODEL := Nanostation 5 (XS5)
|
||||
IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkfwimage XS5 -v XS5.ar2313
|
||||
DEFAULT := n
|
||||
endef
|
||||
TARGET_DEVICES += ubnt_nanostation-5
|
||||
|
||||
define Device/compex_np25g
|
||||
DEVICE_VENDOR := Compex
|
||||
DEVICE_MODEL := NP25G
|
||||
KERNEL := kernel-bin | gzip-kernel
|
||||
IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkmylofw np25g
|
||||
BROKEN := y
|
||||
endef
|
||||
TARGET_DEVICES += compex_np25g
|
||||
|
||||
define Device/compex_wpe53g
|
||||
DEVICE_VENDOR := Compex
|
||||
DEVICE_MODEL := WPE53G
|
||||
KERNEL := kernel-bin | gzip-kernel
|
||||
IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkmylofw wpe53g
|
||||
BROKEN := y
|
||||
endef
|
||||
TARGET_DEVICES += compex_wpe53g
|
||||
|
||||
$(eval $(call BuildImage))
|
||||
212
ath25/patches-5.15/107-ar5312_gpio.patch
Normal file
212
ath25/patches-5.15/107-ar5312_gpio.patch
Normal file
@ -0,0 +1,212 @@
|
||||
--- a/arch/mips/ath25/Kconfig
|
||||
+++ b/arch/mips/ath25/Kconfig
|
||||
@@ -2,6 +2,7 @@
|
||||
config SOC_AR5312
|
||||
bool "Atheros AR5312/AR2312+ SoC support"
|
||||
depends on ATH25
|
||||
+ select GPIO_AR5312
|
||||
default y
|
||||
|
||||
config SOC_AR2315
|
||||
--- a/arch/mips/ath25/ar5312.c
|
||||
+++ b/arch/mips/ath25/ar5312.c
|
||||
@@ -23,6 +23,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/reboot.h>
|
||||
+#include <linux/gpio.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
@@ -177,6 +178,22 @@ static struct platform_device ar5312_phy
|
||||
.num_resources = 1,
|
||||
};
|
||||
|
||||
+static struct resource ar5312_gpio_res[] = {
|
||||
+ {
|
||||
+ .name = "ar5312-gpio",
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ .start = AR5312_GPIO_BASE,
|
||||
+ .end = AR5312_GPIO_BASE + AR5312_GPIO_SIZE - 1,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct platform_device ar5312_gpio = {
|
||||
+ .name = "ar5312-gpio",
|
||||
+ .id = -1,
|
||||
+ .resource = ar5312_gpio_res,
|
||||
+ .num_resources = ARRAY_SIZE(ar5312_gpio_res),
|
||||
+};
|
||||
+
|
||||
static void __init ar5312_flash_init(void)
|
||||
{
|
||||
void __iomem *flashctl_base;
|
||||
@@ -244,6 +261,8 @@ void __init ar5312_init_devices(void)
|
||||
|
||||
platform_device_register(&ar5312_physmap_flash);
|
||||
|
||||
+ platform_device_register(&ar5312_gpio);
|
||||
+
|
||||
switch (ath25_soc) {
|
||||
case ATH25_SOC_AR5312:
|
||||
if (!ath25_board.radio)
|
||||
--- a/drivers/gpio/Kconfig
|
||||
+++ b/drivers/gpio/Kconfig
|
||||
@@ -143,6 +143,13 @@ config GPIO_AMDPT
|
||||
driver for GPIO functionality on Promontory IOHub
|
||||
Require ACPI ASL code to enumerate as a platform device.
|
||||
|
||||
+config GPIO_AR5312
|
||||
+ bool "AR5312 SoC GPIO support"
|
||||
+ default y if SOC_AR5312
|
||||
+ depends on SOC_AR5312
|
||||
+ help
|
||||
+ Say yes here to enable GPIO support for Atheros AR5312/AR2312+ SoCs.
|
||||
+
|
||||
config GPIO_ASPEED
|
||||
tristate "Aspeed GPIO support"
|
||||
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
|
||||
--- a/drivers/gpio/Makefile
|
||||
+++ b/drivers/gpio/Makefile
|
||||
@@ -32,6 +32,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-alt
|
||||
obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
|
||||
obj-$(CONFIG_GPIO_AMD_FCH) += gpio-amd-fch.o
|
||||
obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o
|
||||
+obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
|
||||
obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
|
||||
obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o
|
||||
obj-$(CONFIG_GPIO_ASPEED_SGPIO) += gpio-aspeed-sgpio.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/gpio/gpio-ar5312.c
|
||||
@@ -0,0 +1,121 @@
|
||||
+/*
|
||||
+ * This file is subject to the terms and conditions of the GNU General Public
|
||||
+ * License. See the file "COPYING" in the main directory of this archive
|
||||
+ * for more details.
|
||||
+ *
|
||||
+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
|
||||
+ * Copyright (C) 2006 FON Technology, SL.
|
||||
+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
|
||||
+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/gpio.h>
|
||||
+
|
||||
+#define DRIVER_NAME "ar5312-gpio"
|
||||
+
|
||||
+#define AR5312_GPIO_DO 0x00 /* output register */
|
||||
+#define AR5312_GPIO_DI 0x04 /* intput register */
|
||||
+#define AR5312_GPIO_CR 0x08 /* control register */
|
||||
+
|
||||
+#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
|
||||
+#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
|
||||
+#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
|
||||
+#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
|
||||
+#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
|
||||
+
|
||||
+#define AR5312_GPIO_NUM 8
|
||||
+
|
||||
+static void __iomem *ar5312_mem;
|
||||
+
|
||||
+static inline u32 ar5312_gpio_reg_read(unsigned reg)
|
||||
+{
|
||||
+ return __raw_readl(ar5312_mem + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void ar5312_gpio_reg_write(unsigned reg, u32 val)
|
||||
+{
|
||||
+ __raw_writel(val, ar5312_mem + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void ar5312_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
|
||||
+{
|
||||
+ ar5312_gpio_reg_write(reg, (ar5312_gpio_reg_read(reg) & ~mask) | val);
|
||||
+}
|
||||
+
|
||||
+static int ar5312_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
|
||||
+{
|
||||
+ return (ar5312_gpio_reg_read(AR5312_GPIO_DI) >> gpio) & 1;
|
||||
+}
|
||||
+
|
||||
+static void ar5312_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
|
||||
+{
|
||||
+ u32 reg = ar5312_gpio_reg_read(AR5312_GPIO_DO);
|
||||
+
|
||||
+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
|
||||
+ ar5312_gpio_reg_write(AR5312_GPIO_DO, reg);
|
||||
+}
|
||||
+
|
||||
+static int ar5312_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
|
||||
+{
|
||||
+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 0, 1 << gpio);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ar5312_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
|
||||
+{
|
||||
+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 1 << gpio, 0);
|
||||
+ ar5312_gpio_set_val(chip, gpio, val);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct gpio_chip ar5312_gpio_chip = {
|
||||
+ .label = DRIVER_NAME,
|
||||
+ .direction_input = ar5312_gpio_dir_in,
|
||||
+ .direction_output = ar5312_gpio_dir_out,
|
||||
+ .set = ar5312_gpio_set_val,
|
||||
+ .get = ar5312_gpio_get_val,
|
||||
+ .base = 0,
|
||||
+ .ngpio = AR5312_GPIO_NUM,
|
||||
+};
|
||||
+
|
||||
+static int ar5312_gpio_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct resource *res;
|
||||
+ int ret;
|
||||
+
|
||||
+ if (ar5312_mem)
|
||||
+ return -EBUSY;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ ar5312_mem = devm_ioremap_resource(dev, res);
|
||||
+ if (IS_ERR(ar5312_mem))
|
||||
+ return PTR_ERR(ar5312_mem);
|
||||
+
|
||||
+ ar5312_gpio_chip.parent = dev;
|
||||
+ ret = gpiochip_add(&ar5312_gpio_chip);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to add gpiochip\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver ar5312_gpio_driver = {
|
||||
+ .probe = ar5312_gpio_probe,
|
||||
+ .driver = {
|
||||
+ .name = DRIVER_NAME,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
+static int __init ar5312_gpio_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&ar5312_gpio_driver);
|
||||
+}
|
||||
+subsys_initcall(ar5312_gpio_init);
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -232,6 +232,7 @@ config ATH25
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select DMA_NONCOHERENT
|
||||
+ select GPIOLIB
|
||||
select IRQ_MIPS_CPU
|
||||
select IRQ_DOMAIN
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
363
ath25/patches-5.15/108-ar2315_gpio.patch
Normal file
363
ath25/patches-5.15/108-ar2315_gpio.patch
Normal file
@ -0,0 +1,363 @@
|
||||
--- a/arch/mips/ath25/Kconfig
|
||||
+++ b/arch/mips/ath25/Kconfig
|
||||
@@ -8,6 +8,7 @@ config SOC_AR5312
|
||||
config SOC_AR2315
|
||||
bool "Atheros AR2315+ SoC support"
|
||||
depends on ATH25
|
||||
+ select GPIO_AR2315
|
||||
default y
|
||||
|
||||
config PCI_AR2315
|
||||
--- a/arch/mips/ath25/ar2315.c
|
||||
+++ b/arch/mips/ath25/ar2315.c
|
||||
@@ -22,6 +22,8 @@
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reboot.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/gpio.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
@@ -165,11 +167,42 @@ void __init ar2315_arch_init_irq(void)
|
||||
ar2315_misc_irq_domain = domain;
|
||||
}
|
||||
|
||||
+static struct resource ar2315_gpio_res[] = {
|
||||
+ {
|
||||
+ .name = "ar2315-gpio",
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ .start = AR2315_RST_BASE + AR2315_GPIO,
|
||||
+ .end = AR2315_RST_BASE + AR2315_GPIO + 0x10 - 1,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "ar2315-gpio",
|
||||
+ .flags = IORESOURCE_IRQ,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "ar2315-gpio-irq-base",
|
||||
+ .flags = IORESOURCE_IRQ,
|
||||
+ .start = AR231X_GPIO_IRQ_BASE,
|
||||
+ .end = AR231X_GPIO_IRQ_BASE,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
+static struct platform_device ar2315_gpio = {
|
||||
+ .id = -1,
|
||||
+ .name = "ar2315-gpio",
|
||||
+ .resource = ar2315_gpio_res,
|
||||
+ .num_resources = ARRAY_SIZE(ar2315_gpio_res)
|
||||
+};
|
||||
+
|
||||
void __init ar2315_init_devices(void)
|
||||
{
|
||||
/* Find board configuration */
|
||||
ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
|
||||
|
||||
+ ar2315_gpio_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
|
||||
+ AR2315_MISC_IRQ_GPIO);
|
||||
+ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
|
||||
+ platform_device_register(&ar2315_gpio);
|
||||
+
|
||||
ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
|
||||
}
|
||||
|
||||
@@ -185,8 +218,8 @@ static void ar2315_restart(char *command
|
||||
/* Cold reset does not work on the AR2315/6, use the GPIO reset bits
|
||||
* a workaround. Give it some time to attempt a gpio based hardware
|
||||
* reset (atheros reference design workaround) */
|
||||
-
|
||||
- /* TODO: implement the GPIO reset workaround */
|
||||
+ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
|
||||
+ mdelay(100);
|
||||
|
||||
/* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
|
||||
* workaround. Attempt to jump to the mips reset location -
|
||||
--- a/drivers/gpio/Kconfig
|
||||
+++ b/drivers/gpio/Kconfig
|
||||
@@ -143,6 +143,13 @@ config GPIO_AMDPT
|
||||
driver for GPIO functionality on Promontory IOHub
|
||||
Require ACPI ASL code to enumerate as a platform device.
|
||||
|
||||
+config GPIO_AR2315
|
||||
+ bool "AR2315 SoC GPIO support"
|
||||
+ default y if SOC_AR2315
|
||||
+ depends on SOC_AR2315
|
||||
+ help
|
||||
+ Say yes here to enable GPIO support for Atheros AR2315+ SoCs.
|
||||
+
|
||||
config GPIO_AR5312
|
||||
bool "AR5312 SoC GPIO support"
|
||||
default y if SOC_AR5312
|
||||
--- a/drivers/gpio/Makefile
|
||||
+++ b/drivers/gpio/Makefile
|
||||
@@ -32,6 +32,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-alt
|
||||
obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
|
||||
obj-$(CONFIG_GPIO_AMD_FCH) += gpio-amd-fch.o
|
||||
obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o
|
||||
+obj-$(CONFIG_GPIO_AR2315) += gpio-ar2315.o
|
||||
obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
|
||||
obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
|
||||
obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/gpio/gpio-ar2315.c
|
||||
@@ -0,0 +1,233 @@
|
||||
+/*
|
||||
+ * This file is subject to the terms and conditions of the GNU General Public
|
||||
+ * License. See the file "COPYING" in the main directory of this archive
|
||||
+ * for more details.
|
||||
+ *
|
||||
+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
|
||||
+ * Copyright (C) 2006 FON Technology, SL.
|
||||
+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>
|
||||
+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/gpio.h>
|
||||
+#include <linux/irq.h>
|
||||
+
|
||||
+#define DRIVER_NAME "ar2315-gpio"
|
||||
+
|
||||
+#define AR2315_GPIO_DI 0x0000
|
||||
+#define AR2315_GPIO_DO 0x0008
|
||||
+#define AR2315_GPIO_DIR 0x0010
|
||||
+#define AR2315_GPIO_INT 0x0018
|
||||
+
|
||||
+#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
|
||||
+#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
|
||||
+#define AR2315_GPIO_DIR_I(x) (0) /* input */
|
||||
+
|
||||
+#define AR2315_GPIO_INT_NUM_M 0x3F /* mask for GPIO num */
|
||||
+#define AR2315_GPIO_INT_TRIG(x) ((x) << 6) /* interrupt trigger */
|
||||
+#define AR2315_GPIO_INT_TRIG_M (0x3 << 6) /* mask for int trig */
|
||||
+
|
||||
+#define AR2315_GPIO_INT_TRIG_OFF 0 /* Triggerring off */
|
||||
+#define AR2315_GPIO_INT_TRIG_LOW 1 /* Low Level Triggered */
|
||||
+#define AR2315_GPIO_INT_TRIG_HIGH 2 /* High Level Triggered */
|
||||
+#define AR2315_GPIO_INT_TRIG_EDGE 3 /* Edge Triggered */
|
||||
+
|
||||
+#define AR2315_GPIO_NUM 22
|
||||
+
|
||||
+static u32 ar2315_gpio_intmask;
|
||||
+static u32 ar2315_gpio_intval;
|
||||
+static unsigned ar2315_gpio_irq_base;
|
||||
+static void __iomem *ar2315_mem;
|
||||
+
|
||||
+static inline u32 ar2315_gpio_reg_read(unsigned reg)
|
||||
+{
|
||||
+ return __raw_readl(ar2315_mem + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void ar2315_gpio_reg_write(unsigned reg, u32 val)
|
||||
+{
|
||||
+ __raw_writel(val, ar2315_mem + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
|
||||
+{
|
||||
+ ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val);
|
||||
+}
|
||||
+
|
||||
+static void ar2315_gpio_irq_handler(struct irq_desc *desc)
|
||||
+{
|
||||
+ u32 pend;
|
||||
+ int bit = -1;
|
||||
+
|
||||
+ /* only do one gpio interrupt at a time */
|
||||
+ pend = ar2315_gpio_reg_read(AR2315_GPIO_DI);
|
||||
+ pend ^= ar2315_gpio_intval;
|
||||
+ pend &= ar2315_gpio_intmask;
|
||||
+
|
||||
+ if (pend) {
|
||||
+ bit = fls(pend) - 1;
|
||||
+ pend &= ~(1 << bit);
|
||||
+ ar2315_gpio_intval ^= (1 << bit);
|
||||
+ }
|
||||
+
|
||||
+ /* Enable interrupt with edge detection */
|
||||
+ if ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
|
||||
+ AR2315_GPIO_DIR_I(bit))
|
||||
+ return;
|
||||
+
|
||||
+ if (bit >= 0)
|
||||
+ generic_handle_irq(ar2315_gpio_irq_base + bit);
|
||||
+}
|
||||
+
|
||||
+static void ar2315_gpio_int_setup(unsigned gpio, int trig)
|
||||
+{
|
||||
+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT);
|
||||
+
|
||||
+ reg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M);
|
||||
+ reg |= gpio | AR2315_GPIO_INT_TRIG(trig);
|
||||
+ ar2315_gpio_reg_write(AR2315_GPIO_INT, reg);
|
||||
+}
|
||||
+
|
||||
+static void ar2315_gpio_irq_unmask(struct irq_data *d)
|
||||
+{
|
||||
+ unsigned gpio = d->irq - ar2315_gpio_irq_base;
|
||||
+ u32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR);
|
||||
+
|
||||
+ /* Enable interrupt with edge detection */
|
||||
+ if ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio))
|
||||
+ return;
|
||||
+
|
||||
+ ar2315_gpio_intmask |= (1 << gpio);
|
||||
+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE);
|
||||
+}
|
||||
+
|
||||
+static void ar2315_gpio_irq_mask(struct irq_data *d)
|
||||
+{
|
||||
+ unsigned gpio = d->irq - ar2315_gpio_irq_base;
|
||||
+
|
||||
+ /* Disable interrupt */
|
||||
+ ar2315_gpio_intmask &= ~(1 << gpio);
|
||||
+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF);
|
||||
+}
|
||||
+
|
||||
+static struct irq_chip ar2315_gpio_irq_chip = {
|
||||
+ .name = DRIVER_NAME,
|
||||
+ .irq_unmask = ar2315_gpio_irq_unmask,
|
||||
+ .irq_mask = ar2315_gpio_irq_mask,
|
||||
+};
|
||||
+
|
||||
+static void ar2315_gpio_irq_init(unsigned irq)
|
||||
+{
|
||||
+ unsigned i;
|
||||
+
|
||||
+ ar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI);
|
||||
+ for (i = 0; i < AR2315_GPIO_NUM; i++) {
|
||||
+ unsigned _irq = ar2315_gpio_irq_base + i;
|
||||
+
|
||||
+ irq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip,
|
||||
+ handle_level_irq);
|
||||
+ }
|
||||
+ irq_set_chained_handler(irq, ar2315_gpio_irq_handler);
|
||||
+}
|
||||
+
|
||||
+static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
|
||||
+{
|
||||
+ return (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1;
|
||||
+}
|
||||
+
|
||||
+static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
|
||||
+{
|
||||
+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO);
|
||||
+
|
||||
+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
|
||||
+ ar2315_gpio_reg_write(AR2315_GPIO_DO, reg);
|
||||
+}
|
||||
+
|
||||
+static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
|
||||
+{
|
||||
+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
|
||||
+{
|
||||
+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio);
|
||||
+ ar2315_gpio_set_val(chip, gpio, val);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
|
||||
+{
|
||||
+ return ar2315_gpio_irq_base + gpio;
|
||||
+}
|
||||
+
|
||||
+static struct gpio_chip ar2315_gpio_chip = {
|
||||
+ .label = DRIVER_NAME,
|
||||
+ .direction_input = ar2315_gpio_dir_in,
|
||||
+ .direction_output = ar2315_gpio_dir_out,
|
||||
+ .set = ar2315_gpio_set_val,
|
||||
+ .get = ar2315_gpio_get_val,
|
||||
+ .to_irq = ar2315_gpio_to_irq,
|
||||
+ .base = 0,
|
||||
+ .ngpio = AR2315_GPIO_NUM,
|
||||
+};
|
||||
+
|
||||
+static int ar2315_gpio_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct resource *res;
|
||||
+ unsigned irq;
|
||||
+ int ret;
|
||||
+
|
||||
+ if (ar2315_mem)
|
||||
+ return -EBUSY;
|
||||
+
|
||||
+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
|
||||
+ "ar2315-gpio-irq-base");
|
||||
+ if (!res) {
|
||||
+ dev_err(dev, "not found GPIO IRQ base\n");
|
||||
+ return -ENXIO;
|
||||
+ }
|
||||
+ ar2315_gpio_irq_base = res->start;
|
||||
+
|
||||
+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME);
|
||||
+ if (!res) {
|
||||
+ dev_err(dev, "not found IRQ number\n");
|
||||
+ return -ENXIO;
|
||||
+ }
|
||||
+ irq = res->start;
|
||||
+
|
||||
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME);
|
||||
+ ar2315_mem = devm_ioremap_resource(dev, res);
|
||||
+ if (IS_ERR(ar2315_mem))
|
||||
+ return PTR_ERR(ar2315_mem);
|
||||
+
|
||||
+ ar2315_gpio_chip.parent = dev;
|
||||
+ ret = gpiochip_add(&ar2315_gpio_chip);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to add gpiochip\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ar2315_gpio_irq_init(irq);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver ar2315_gpio_driver = {
|
||||
+ .probe = ar2315_gpio_probe,
|
||||
+ .driver = {
|
||||
+ .name = DRIVER_NAME,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
+static int __init ar2315_gpio_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&ar2315_gpio_driver);
|
||||
+}
|
||||
+subsys_initcall(ar2315_gpio_init);
|
||||
--- a/arch/mips/ath25/devices.h
|
||||
+++ b/arch/mips/ath25/devices.h
|
||||
@@ -4,6 +4,11 @@
|
||||
|
||||
#include <linux/cpu.h>
|
||||
|
||||
+#define AR231X_GPIO_IRQ_BASE 0x30
|
||||
+
|
||||
+/* GPIO number for AR2315/16 reset issue workaround */
|
||||
+#define AR2315_RESET_GPIO 5
|
||||
+
|
||||
#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
|
||||
|
||||
#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
|
||||
--- a/arch/mips/ath25/ar2315_regs.h
|
||||
+++ b/arch/mips/ath25/ar2315_regs.h
|
||||
@@ -315,6 +315,9 @@
|
||||
#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
|
||||
#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
|
||||
|
||||
+/* GPIO MMR base address */
|
||||
+#define AR2315_GPIO 0x0088
|
||||
+
|
||||
/*
|
||||
* Local Bus Interface Registers
|
||||
*/
|
||||
1733
ath25/patches-5.15/110-ar2313_ethernet.patch
Normal file
1733
ath25/patches-5.15/110-ar2313_ethernet.patch
Normal file
File diff suppressed because it is too large
Load Diff
631
ath25/patches-5.15/120-spiflash.patch
Normal file
631
ath25/patches-5.15/120-spiflash.patch
Normal file
@ -0,0 +1,631 @@
|
||||
--- a/drivers/mtd/devices/Kconfig
|
||||
+++ b/drivers/mtd/devices/Kconfig
|
||||
@@ -120,6 +120,10 @@ config MTD_BCM47XXSFLASH
|
||||
registered by bcma as platform devices. This enables driver for
|
||||
serial flash memories.
|
||||
|
||||
+config MTD_AR2315
|
||||
+ tristate "Atheros AR2315+ SPI Flash support"
|
||||
+ depends on SOC_AR2315
|
||||
+
|
||||
config MTD_SLRAM
|
||||
tristate "Uncached system RAM"
|
||||
help
|
||||
--- a/drivers/mtd/devices/Makefile
|
||||
+++ b/drivers/mtd/devices/Makefile
|
||||
@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_MCHP23K256) += mchp23k2
|
||||
obj-$(CONFIG_MTD_MCHP48L640) += mchp48l640.o
|
||||
obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
|
||||
obj-$(CONFIG_MTD_SST25L) += sst25l.o
|
||||
+obj-$(CONFIG_MTD_AR2315) += ar2315.o
|
||||
obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
|
||||
obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o
|
||||
obj-$(CONFIG_MTD_POWERNV_FLASH) += powernv_flash.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/mtd/devices/ar2315.c
|
||||
@@ -0,0 +1,456 @@
|
||||
+
|
||||
+/*
|
||||
+ * MTD driver for the SPI Flash Memory support on Atheros AR2315
|
||||
+ *
|
||||
+ * Copyright (c) 2005-2006 Atheros Communications Inc.
|
||||
+ * Copyright (C) 2006-2007 FON Technology, SL.
|
||||
+ * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
|
||||
+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
|
||||
+ *
|
||||
+ * This code is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/errno.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/mtd/mtd.h>
|
||||
+#include <linux/mtd/partitions.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/sched.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/mutex.h>
|
||||
+
|
||||
+#include "ar2315_spiflash.h"
|
||||
+
|
||||
+#define DRIVER_NAME "ar2315-spiflash"
|
||||
+
|
||||
+#define busy_wait(_priv, _condition, _wait) do { \
|
||||
+ while (_condition) { \
|
||||
+ if (_wait > 1) \
|
||||
+ msleep(_wait); \
|
||||
+ else if ((_wait == 1) && need_resched()) \
|
||||
+ schedule(); \
|
||||
+ else \
|
||||
+ udelay(1); \
|
||||
+ } \
|
||||
+} while (0)
|
||||
+
|
||||
+enum {
|
||||
+ FLASH_NONE,
|
||||
+ FLASH_1MB,
|
||||
+ FLASH_2MB,
|
||||
+ FLASH_4MB,
|
||||
+ FLASH_8MB,
|
||||
+ FLASH_16MB,
|
||||
+};
|
||||
+
|
||||
+/* Flash configuration table */
|
||||
+struct flashconfig {
|
||||
+ u32 byte_cnt;
|
||||
+ u32 sector_cnt;
|
||||
+ u32 sector_size;
|
||||
+};
|
||||
+
|
||||
+static const struct flashconfig flashconfig_tbl[] = {
|
||||
+ [FLASH_NONE] = { 0, 0, 0},
|
||||
+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
|
||||
+ STM_1MB_SECTOR_SIZE},
|
||||
+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
|
||||
+ STM_2MB_SECTOR_SIZE},
|
||||
+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
|
||||
+ STM_4MB_SECTOR_SIZE},
|
||||
+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
|
||||
+ STM_8MB_SECTOR_SIZE},
|
||||
+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
|
||||
+ STM_16MB_SECTOR_SIZE}
|
||||
+};
|
||||
+
|
||||
+/* Mapping of generic opcodes to STM serial flash opcodes */
|
||||
+enum {
|
||||
+ SPI_WRITE_ENABLE,
|
||||
+ SPI_WRITE_DISABLE,
|
||||
+ SPI_RD_STATUS,
|
||||
+ SPI_WR_STATUS,
|
||||
+ SPI_RD_DATA,
|
||||
+ SPI_FAST_RD_DATA,
|
||||
+ SPI_PAGE_PROGRAM,
|
||||
+ SPI_SECTOR_ERASE,
|
||||
+ SPI_BULK_ERASE,
|
||||
+ SPI_DEEP_PWRDOWN,
|
||||
+ SPI_RD_SIG,
|
||||
+};
|
||||
+
|
||||
+struct opcodes {
|
||||
+ __u16 code;
|
||||
+ __s8 tx_cnt;
|
||||
+ __s8 rx_cnt;
|
||||
+};
|
||||
+
|
||||
+static const struct opcodes stm_opcodes[] = {
|
||||
+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
|
||||
+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
|
||||
+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
|
||||
+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
|
||||
+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
|
||||
+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
|
||||
+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
|
||||
+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
|
||||
+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
|
||||
+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
|
||||
+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
|
||||
+};
|
||||
+
|
||||
+/* Driver private data structure */
|
||||
+struct spiflash_priv {
|
||||
+ struct mtd_info mtd;
|
||||
+ void __iomem *readaddr; /* memory mapped data for read */
|
||||
+ void __iomem *mmraddr; /* memory mapped register space */
|
||||
+ struct mutex lock; /* serialize registers access */
|
||||
+};
|
||||
+
|
||||
+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
|
||||
+
|
||||
+enum {
|
||||
+ FL_READY,
|
||||
+ FL_READING,
|
||||
+ FL_ERASING,
|
||||
+ FL_WRITING
|
||||
+};
|
||||
+
|
||||
+/*****************************************************************************/
|
||||
+
|
||||
+static u32
|
||||
+spiflash_read_reg(struct spiflash_priv *priv, int reg)
|
||||
+{
|
||||
+ return ioread32(priv->mmraddr + reg);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
|
||||
+{
|
||||
+ iowrite32(data, priv->mmraddr + reg);
|
||||
+}
|
||||
+
|
||||
+static u32
|
||||
+spiflash_wait_busy(struct spiflash_priv *priv)
|
||||
+{
|
||||
+ u32 reg;
|
||||
+
|
||||
+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
|
||||
+ SPI_CTL_BUSY, 0);
|
||||
+ return reg;
|
||||
+}
|
||||
+
|
||||
+static u32
|
||||
+spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
|
||||
+{
|
||||
+ const struct opcodes *op;
|
||||
+ u32 reg, mask;
|
||||
+
|
||||
+ op = &stm_opcodes[opcode];
|
||||
+ reg = spiflash_wait_busy(priv);
|
||||
+ spiflash_write_reg(priv, SPI_FLASH_OPCODE,
|
||||
+ ((u32)op->code) | (addr << 8));
|
||||
+
|
||||
+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
|
||||
+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
|
||||
+
|
||||
+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
|
||||
+ spiflash_wait_busy(priv);
|
||||
+
|
||||
+ if (!op->rx_cnt)
|
||||
+ return 0;
|
||||
+
|
||||
+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
|
||||
+
|
||||
+ switch (op->rx_cnt) {
|
||||
+ case 1:
|
||||
+ mask = 0x000000ff;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ mask = 0x0000ffff;
|
||||
+ break;
|
||||
+ case 3:
|
||||
+ mask = 0x00ffffff;
|
||||
+ break;
|
||||
+ default:
|
||||
+ mask = 0xffffffff;
|
||||
+ break;
|
||||
+ }
|
||||
+ reg &= mask;
|
||||
+
|
||||
+ return reg;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Probe SPI flash device
|
||||
+ * Function returns 0 for failure.
|
||||
+ * and flashconfig_tbl array index for success.
|
||||
+ */
|
||||
+static int
|
||||
+spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv)
|
||||
+{
|
||||
+ u32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
|
||||
+ int flash_size;
|
||||
+
|
||||
+ switch (sig) {
|
||||
+ case STM_8MBIT_SIGNATURE:
|
||||
+ flash_size = FLASH_1MB;
|
||||
+ break;
|
||||
+ case STM_16MBIT_SIGNATURE:
|
||||
+ flash_size = FLASH_2MB;
|
||||
+ break;
|
||||
+ case STM_32MBIT_SIGNATURE:
|
||||
+ flash_size = FLASH_4MB;
|
||||
+ break;
|
||||
+ case STM_64MBIT_SIGNATURE:
|
||||
+ flash_size = FLASH_8MB;
|
||||
+ break;
|
||||
+ case STM_128MBIT_SIGNATURE:
|
||||
+ flash_size = FLASH_16MB;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_warn(&pdev->dev, "read of flash device signature failed!\n");
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ return flash_size;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
|
||||
+{
|
||||
+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
|
||||
+ SPI_STATUS_WIP, timeout);
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
|
||||
+{
|
||||
+ struct spiflash_priv *priv = to_spiflash(mtd);
|
||||
+ const struct opcodes *op;
|
||||
+ u32 temp, reg;
|
||||
+
|
||||
+ if (instr->addr + instr->len > mtd->size)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ mutex_lock(&priv->lock);
|
||||
+
|
||||
+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
|
||||
+ reg = spiflash_wait_busy(priv);
|
||||
+
|
||||
+ op = &stm_opcodes[SPI_SECTOR_ERASE];
|
||||
+ temp = ((u32)instr->addr << 8) | (u32)(op->code);
|
||||
+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
|
||||
+
|
||||
+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
|
||||
+ reg |= op->tx_cnt | SPI_CTL_START;
|
||||
+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
|
||||
+
|
||||
+ spiflash_wait_complete(priv, 20);
|
||||
+
|
||||
+ mutex_unlock(&priv->lock);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
|
||||
+ u_char *buf)
|
||||
+{
|
||||
+ struct spiflash_priv *priv = to_spiflash(mtd);
|
||||
+
|
||||
+ if (!len)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (from + len > mtd->size)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ *retlen = len;
|
||||
+
|
||||
+ mutex_lock(&priv->lock);
|
||||
+
|
||||
+ memcpy_fromio(buf, priv->readaddr + from, len);
|
||||
+
|
||||
+ mutex_unlock(&priv->lock);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
|
||||
+ const u8 *buf)
|
||||
+{
|
||||
+ struct spiflash_priv *priv = to_spiflash(mtd);
|
||||
+ u32 opcode, bytes_left;
|
||||
+
|
||||
+ *retlen = 0;
|
||||
+
|
||||
+ if (!len)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (to + len > mtd->size)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ bytes_left = len;
|
||||
+
|
||||
+ do {
|
||||
+ u32 read_len, reg, page_offset, spi_data = 0;
|
||||
+
|
||||
+ read_len = min(bytes_left, sizeof(u32));
|
||||
+
|
||||
+ /* 32-bit writes cannot span across a page boundary
|
||||
+ * (256 bytes). This types of writes require two page
|
||||
+ * program operations to handle it correctly. The STM part
|
||||
+ * will write the overflow data to the beginning of the
|
||||
+ * current page as opposed to the subsequent page.
|
||||
+ */
|
||||
+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
|
||||
+
|
||||
+ if (page_offset > STM_PAGE_SIZE)
|
||||
+ read_len -= (page_offset - STM_PAGE_SIZE);
|
||||
+
|
||||
+ mutex_lock(&priv->lock);
|
||||
+
|
||||
+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
|
||||
+ spi_data = 0;
|
||||
+ switch (read_len) {
|
||||
+ case 4:
|
||||
+ spi_data |= buf[3] << 24;
|
||||
+ fallthrough;
|
||||
+ case 3:
|
||||
+ spi_data |= buf[2] << 16;
|
||||
+ fallthrough;
|
||||
+ case 2:
|
||||
+ spi_data |= buf[1] << 8;
|
||||
+ fallthrough;
|
||||
+ case 1:
|
||||
+ spi_data |= buf[0] & 0xff;
|
||||
+ break;
|
||||
+ default:
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
|
||||
+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
|
||||
+ (to & 0x00ffffff) << 8;
|
||||
+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
|
||||
+
|
||||
+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
|
||||
+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
|
||||
+ reg |= (read_len + 4) | SPI_CTL_START;
|
||||
+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
|
||||
+
|
||||
+ spiflash_wait_complete(priv, 1);
|
||||
+
|
||||
+ mutex_unlock(&priv->lock);
|
||||
+
|
||||
+ bytes_left -= read_len;
|
||||
+ to += read_len;
|
||||
+ buf += read_len;
|
||||
+
|
||||
+ *retlen += read_len;
|
||||
+ } while (bytes_left != 0);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
|
||||
+static const char * const part_probe_types[] = {
|
||||
+ "cmdlinepart", "RedBoot", "MyLoader", NULL
|
||||
+};
|
||||
+#endif
|
||||
+
|
||||
+static int
|
||||
+spiflash_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct spiflash_priv *priv;
|
||||
+ struct mtd_info *mtd;
|
||||
+ struct resource *res;
|
||||
+ int index;
|
||||
+ int result = 0;
|
||||
+
|
||||
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ mutex_init(&priv->lock);
|
||||
+ mtd = &priv->mtd;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
+ priv->mmraddr = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(priv->mmraddr)) {
|
||||
+ dev_warn(&pdev->dev, "failed to map flash MMR\n");
|
||||
+ return PTR_ERR(priv->mmraddr);
|
||||
+ }
|
||||
+
|
||||
+ index = spiflash_probe_chip(pdev, priv);
|
||||
+ if (!index) {
|
||||
+ dev_warn(&pdev->dev, "found no flash device\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ priv->readaddr = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(priv->readaddr)) {
|
||||
+ dev_warn(&pdev->dev, "failed to map flash read mem\n");
|
||||
+ return PTR_ERR(priv->readaddr);
|
||||
+ }
|
||||
+
|
||||
+ platform_set_drvdata(pdev, priv);
|
||||
+ mtd->name = "spiflash";
|
||||
+ mtd->type = MTD_NORFLASH;
|
||||
+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
|
||||
+ mtd->size = flashconfig_tbl[index].byte_cnt;
|
||||
+ mtd->erasesize = flashconfig_tbl[index].sector_size;
|
||||
+ mtd->writesize = 1;
|
||||
+ mtd->numeraseregions = 0;
|
||||
+ mtd->eraseregions = NULL;
|
||||
+ mtd->_erase = spiflash_erase;
|
||||
+ mtd->_read = spiflash_read;
|
||||
+ mtd->_write = spiflash_write;
|
||||
+ mtd->owner = THIS_MODULE;
|
||||
+
|
||||
+ dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
|
||||
+
|
||||
+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
|
||||
+ /* parse redboot partitions */
|
||||
+
|
||||
+ result = mtd_device_parse_register(mtd, part_probe_types,
|
||||
+ NULL, NULL, 0);
|
||||
+#endif
|
||||
+
|
||||
+ return result;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+spiflash_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct spiflash_priv *priv = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ mtd_device_unregister(&priv->mtd);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver spiflash_driver = {
|
||||
+ .driver.name = DRIVER_NAME,
|
||||
+ .probe = spiflash_probe,
|
||||
+ .remove = spiflash_remove,
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(spiflash_driver);
|
||||
+
|
||||
+MODULE_LICENSE("GPL");
|
||||
+MODULE_AUTHOR("OpenWrt.org");
|
||||
+MODULE_AUTHOR("Atheros Communications Inc");
|
||||
+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros AR2315+ SOC");
|
||||
+MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
+
|
||||
--- /dev/null
|
||||
+++ b/drivers/mtd/devices/ar2315_spiflash.h
|
||||
@@ -0,0 +1,106 @@
|
||||
+/*
|
||||
+ * Atheros AR2315 SPI Flash Memory support header file.
|
||||
+ *
|
||||
+ * Copyright (c) 2005, Atheros Communications Inc.
|
||||
+ * Copyright (C) 2006 FON Technology, SL.
|
||||
+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
|
||||
+ *
|
||||
+ * This code is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#ifndef __AR2315_SPIFLASH_H
|
||||
+#define __AR2315_SPIFLASH_H
|
||||
+
|
||||
+#define STM_PAGE_SIZE 256
|
||||
+
|
||||
+#define SFI_WRITE_BUFFER_SIZE 4
|
||||
+#define SFI_FLASH_ADDR_MASK 0x00ffffff
|
||||
+
|
||||
+#define STM_8MBIT_SIGNATURE 0x13
|
||||
+#define STM_M25P80_BYTE_COUNT 1048576
|
||||
+#define STM_M25P80_SECTOR_COUNT 16
|
||||
+#define STM_M25P80_SECTOR_SIZE 0x10000
|
||||
+
|
||||
+#define STM_16MBIT_SIGNATURE 0x14
|
||||
+#define STM_M25P16_BYTE_COUNT 2097152
|
||||
+#define STM_M25P16_SECTOR_COUNT 32
|
||||
+#define STM_M25P16_SECTOR_SIZE 0x10000
|
||||
+
|
||||
+#define STM_32MBIT_SIGNATURE 0x15
|
||||
+#define STM_M25P32_BYTE_COUNT 4194304
|
||||
+#define STM_M25P32_SECTOR_COUNT 64
|
||||
+#define STM_M25P32_SECTOR_SIZE 0x10000
|
||||
+
|
||||
+#define STM_64MBIT_SIGNATURE 0x16
|
||||
+#define STM_M25P64_BYTE_COUNT 8388608
|
||||
+#define STM_M25P64_SECTOR_COUNT 128
|
||||
+#define STM_M25P64_SECTOR_SIZE 0x10000
|
||||
+
|
||||
+#define STM_128MBIT_SIGNATURE 0x17
|
||||
+#define STM_M25P128_BYTE_COUNT 16777216
|
||||
+#define STM_M25P128_SECTOR_COUNT 256
|
||||
+#define STM_M25P128_SECTOR_SIZE 0x10000
|
||||
+
|
||||
+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
|
||||
+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
|
||||
+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
|
||||
+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
|
||||
+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
|
||||
+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
|
||||
+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
|
||||
+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
|
||||
+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
|
||||
+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
|
||||
+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
|
||||
+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
|
||||
+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
|
||||
+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
|
||||
+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
|
||||
+
|
||||
+/*
|
||||
+ * ST Microelectronics Opcodes for Serial Flash
|
||||
+ */
|
||||
+
|
||||
+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
|
||||
+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
|
||||
+#define STM_OP_RD_STATUS 0x05 /* Read Status */
|
||||
+#define STM_OP_WR_STATUS 0x01 /* Write Status */
|
||||
+#define STM_OP_RD_DATA 0x03 /* Read Data */
|
||||
+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
|
||||
+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
|
||||
+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
|
||||
+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
|
||||
+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
|
||||
+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
|
||||
+
|
||||
+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
|
||||
+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
|
||||
+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
|
||||
+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
|
||||
+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
|
||||
+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
|
||||
+
|
||||
+/*
|
||||
+ * SPI Flash Interface Registers
|
||||
+ */
|
||||
+
|
||||
+#define SPI_FLASH_CTL 0x00
|
||||
+#define SPI_FLASH_OPCODE 0x04
|
||||
+#define SPI_FLASH_DATA 0x08
|
||||
+
|
||||
+#define SPI_CTL_START 0x00000100
|
||||
+#define SPI_CTL_BUSY 0x00010000
|
||||
+#define SPI_CTL_TXCNT_MASK 0x0000000f
|
||||
+#define SPI_CTL_RXCNT_MASK 0x000000f0
|
||||
+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
|
||||
+#define SPI_CTL_SIZE_MASK 0x00060000
|
||||
+
|
||||
+#define SPI_CTL_CLK_SEL_MASK 0x03000000
|
||||
+#define SPI_OPCODE_MASK 0x000000ff
|
||||
+
|
||||
+#define SPI_STATUS_WIP STM_STATUS_WIP
|
||||
+
|
||||
+#endif
|
||||
--- a/arch/mips/ath25/ar2315.c
|
||||
+++ b/arch/mips/ath25/ar2315.c
|
||||
@@ -218,6 +218,28 @@ static struct platform_device ar2315_gpi
|
||||
.num_resources = ARRAY_SIZE(ar2315_gpio_res)
|
||||
};
|
||||
|
||||
+static struct resource ar2315_spiflash_res[] = {
|
||||
+ {
|
||||
+ .name = "spiflash_read",
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ .start = AR2315_SPI_READ_BASE,
|
||||
+ .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "spiflash_mmr",
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ .start = AR2315_SPI_MMR_BASE,
|
||||
+ .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct platform_device ar2315_spiflash = {
|
||||
+ .id = 0,
|
||||
+ .name = "ar2315-spiflash",
|
||||
+ .resource = ar2315_spiflash_res,
|
||||
+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
|
||||
+};
|
||||
+
|
||||
void __init ar2315_init_devices(void)
|
||||
{
|
||||
/* Find board configuration */
|
||||
@@ -228,6 +250,8 @@ void __init ar2315_init_devices(void)
|
||||
ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
|
||||
platform_device_register(&ar2315_gpio);
|
||||
|
||||
+ platform_device_register(&ar2315_spiflash);
|
||||
+
|
||||
ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
|
||||
ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
|
||||
AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
|
||||
277
ath25/patches-5.15/130-watchdog.patch
Normal file
277
ath25/patches-5.15/130-watchdog.patch
Normal file
@ -0,0 +1,277 @@
|
||||
--- /dev/null
|
||||
+++ b/drivers/watchdog/ar2315-wtd.c
|
||||
@@ -0,0 +1,209 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License as published by
|
||||
+ * the Free Software Foundation; either version 2 of the License, or
|
||||
+ * (at your option) any later version.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ *
|
||||
+ * You should have received a copy of the GNU General Public License
|
||||
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
+ *
|
||||
+ * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
|
||||
+ * Based on EP93xx and ifxmips wdt driver
|
||||
+ */
|
||||
+
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/moduleparam.h>
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/miscdevice.h>
|
||||
+#include <linux/watchdog.h>
|
||||
+#include <linux/fs.h>
|
||||
+#include <linux/ioport.h>
|
||||
+#include <linux/notifier.h>
|
||||
+#include <linux/reboot.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/uaccess.h>
|
||||
+
|
||||
+#define DRIVER_NAME "ar2315-wdt"
|
||||
+
|
||||
+#define CLOCK_RATE 40000000
|
||||
+#define HEARTBEAT(x) (x < 1 || x > 90 ? 20 : x)
|
||||
+
|
||||
+#define WDT_REG_TIMER 0x00
|
||||
+#define WDT_REG_CTRL 0x04
|
||||
+
|
||||
+#define WDT_CTRL_ACT_NONE 0x00000000 /* No action */
|
||||
+#define WDT_CTRL_ACT_NMI 0x00000001 /* NMI on watchdog */
|
||||
+#define WDT_CTRL_ACT_RESET 0x00000002 /* reset on watchdog */
|
||||
+
|
||||
+static int wdt_timeout = 20;
|
||||
+static int started;
|
||||
+static int in_use;
|
||||
+static void __iomem *wdt_base;
|
||||
+
|
||||
+static inline void ar2315_wdt_wr(unsigned reg, u32 val)
|
||||
+{
|
||||
+ iowrite32(val, wdt_base + reg);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+ar2315_wdt_enable(void)
|
||||
+{
|
||||
+ ar2315_wdt_wr(WDT_REG_TIMER, wdt_timeout * CLOCK_RATE);
|
||||
+}
|
||||
+
|
||||
+static ssize_t
|
||||
+ar2315_wdt_write(struct file *file, const char __user *data, size_t len,
|
||||
+ loff_t *ppos)
|
||||
+{
|
||||
+ if (len)
|
||||
+ ar2315_wdt_enable();
|
||||
+ return len;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ar2315_wdt_open(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ if (in_use)
|
||||
+ return -EBUSY;
|
||||
+ ar2315_wdt_enable();
|
||||
+ in_use = 1;
|
||||
+ started = 1;
|
||||
+ return nonseekable_open(inode, file);
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ar2315_wdt_release(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ in_use = 0;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t
|
||||
+ar2315_wdt_interrupt(int irq, void *dev)
|
||||
+{
|
||||
+ struct platform_device *pdev = (struct platform_device *)dev;
|
||||
+
|
||||
+ if (started) {
|
||||
+ dev_crit(&pdev->dev, "watchdog expired, rebooting system\n");
|
||||
+ emergency_restart();
|
||||
+ } else {
|
||||
+ ar2315_wdt_wr(WDT_REG_CTRL, 0);
|
||||
+ ar2315_wdt_wr(WDT_REG_TIMER, 0);
|
||||
+ }
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+static struct watchdog_info ident = {
|
||||
+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
|
||||
+ .identity = "ar2315 Watchdog",
|
||||
+};
|
||||
+
|
||||
+static long
|
||||
+ar2315_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
+{
|
||||
+ int new_wdt_timeout;
|
||||
+ int ret = -ENOIOCTLCMD;
|
||||
+
|
||||
+ switch (cmd) {
|
||||
+ case WDIOC_GETSUPPORT:
|
||||
+ ret = copy_to_user((void __user *)arg, &ident, sizeof(ident)) ?
|
||||
+ -EFAULT : 0;
|
||||
+ break;
|
||||
+ case WDIOC_KEEPALIVE:
|
||||
+ ar2315_wdt_enable();
|
||||
+ ret = 0;
|
||||
+ break;
|
||||
+ case WDIOC_SETTIMEOUT:
|
||||
+ ret = get_user(new_wdt_timeout, (int __user *)arg);
|
||||
+ if (ret)
|
||||
+ break;
|
||||
+ wdt_timeout = HEARTBEAT(new_wdt_timeout);
|
||||
+ ar2315_wdt_enable();
|
||||
+ break;
|
||||
+ case WDIOC_GETTIMEOUT:
|
||||
+ ret = put_user(wdt_timeout, (int __user *)arg);
|
||||
+ break;
|
||||
+ }
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct file_operations ar2315_wdt_fops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .llseek = no_llseek,
|
||||
+ .write = ar2315_wdt_write,
|
||||
+ .unlocked_ioctl = ar2315_wdt_ioctl,
|
||||
+ .open = ar2315_wdt_open,
|
||||
+ .release = ar2315_wdt_release,
|
||||
+};
|
||||
+
|
||||
+static struct miscdevice ar2315_wdt_miscdev = {
|
||||
+ .minor = WATCHDOG_MINOR,
|
||||
+ .name = "watchdog",
|
||||
+ .fops = &ar2315_wdt_fops,
|
||||
+};
|
||||
+
|
||||
+static int
|
||||
+ar2315_wdt_probe(struct platform_device *dev)
|
||||
+{
|
||||
+ struct resource *mem_res, *irq_res;
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ if (wdt_base)
|
||||
+ return -EBUSY;
|
||||
+
|
||||
+ irq_res = platform_get_resource(dev, IORESOURCE_IRQ, 0);
|
||||
+ if (!irq_res) {
|
||||
+ dev_err(&dev->dev, "no IRQ resource\n");
|
||||
+ return -ENOENT;
|
||||
+ }
|
||||
+
|
||||
+ mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
||||
+ wdt_base = devm_ioremap_resource(&dev->dev, mem_res);
|
||||
+ if (IS_ERR(wdt_base))
|
||||
+ return PTR_ERR(wdt_base);
|
||||
+
|
||||
+ ret = devm_request_irq(&dev->dev, irq_res->start, ar2315_wdt_interrupt,
|
||||
+ 0, DRIVER_NAME, dev);
|
||||
+ if (ret) {
|
||||
+ dev_err(&dev->dev, "failed to register inetrrupt\n");
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
+ ret = misc_register(&ar2315_wdt_miscdev);
|
||||
+ if (ret)
|
||||
+ dev_err(&dev->dev, "failed to register miscdev\n");
|
||||
+
|
||||
+out:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ar2315_wdt_remove(struct platform_device *dev)
|
||||
+{
|
||||
+ misc_deregister(&ar2315_wdt_miscdev);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver ar2315_wdt_driver = {
|
||||
+ .probe = ar2315_wdt_probe,
|
||||
+ .remove = ar2315_wdt_remove,
|
||||
+ .driver = {
|
||||
+ .name = DRIVER_NAME,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(ar2315_wdt_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Atheros AR2315 hardware watchdog driver");
|
||||
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
||||
+MODULE_LICENSE("GPL");
|
||||
+MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
--- a/drivers/watchdog/Kconfig
|
||||
+++ b/drivers/watchdog/Kconfig
|
||||
@@ -1829,6 +1829,13 @@ config PIC32_DMT
|
||||
To compile this driver as a loadable module, choose M here.
|
||||
The module will be called pic32-dmt.
|
||||
|
||||
+config AR2315_WDT
|
||||
+ tristate "Atheros AR2315+ WiSoCs Watchdog Timer"
|
||||
+ depends on ATH25
|
||||
+ help
|
||||
+ Hardware driver for the built-in watchdog timer on the Atheros
|
||||
+ AR2315/AR2316 WiSoCs.
|
||||
+
|
||||
# PARISC Architecture
|
||||
|
||||
# POWERPC Architecture
|
||||
--- a/drivers/watchdog/Makefile
|
||||
+++ b/drivers/watchdog/Makefile
|
||||
@@ -161,6 +161,7 @@ obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o
|
||||
obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
|
||||
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
|
||||
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
|
||||
+obj-$(CONFIG_AR2315_WDT) += ar2315-wtd.o
|
||||
obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
|
||||
obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
|
||||
octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
|
||||
--- a/arch/mips/ath25/ar2315.c
|
||||
+++ b/arch/mips/ath25/ar2315.c
|
||||
@@ -218,6 +218,24 @@ static struct platform_device ar2315_gpi
|
||||
.num_resources = ARRAY_SIZE(ar2315_gpio_res)
|
||||
};
|
||||
|
||||
+static struct resource ar2315_wdt_res[] = {
|
||||
+ {
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ .start = AR2315_RST_BASE + AR2315_WDT_TIMER,
|
||||
+ .end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1,
|
||||
+ },
|
||||
+ {
|
||||
+ .flags = IORESOURCE_IRQ,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
+static struct platform_device ar2315_wdt = {
|
||||
+ .id = 0,
|
||||
+ .name = "ar2315-wdt",
|
||||
+ .resource = ar2315_wdt_res,
|
||||
+ .num_resources = ARRAY_SIZE(ar2315_wdt_res)
|
||||
+};
|
||||
+
|
||||
static struct resource ar2315_spiflash_res[] = {
|
||||
{
|
||||
.name = "spiflash_read",
|
||||
@@ -250,6 +268,11 @@ void __init ar2315_init_devices(void)
|
||||
ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
|
||||
platform_device_register(&ar2315_gpio);
|
||||
|
||||
+ ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
|
||||
+ AR2315_MISC_IRQ_WATCHDOG);
|
||||
+ ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
|
||||
+ platform_device_register(&ar2315_wdt);
|
||||
+
|
||||
platform_device_register(&ar2315_spiflash);
|
||||
|
||||
ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
|
||||
60
ath25/patches-5.15/140-redboot_boardconfig.patch
Normal file
60
ath25/patches-5.15/140-redboot_boardconfig.patch
Normal file
@ -0,0 +1,60 @@
|
||||
--- a/drivers/mtd/parsers/redboot.c
|
||||
+++ b/drivers/mtd/parsers/redboot.c
|
||||
@@ -16,6 +16,8 @@
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
+#define BOARD_CONFIG_PART "boardconfig"
|
||||
+
|
||||
struct fis_image_desc {
|
||||
unsigned char name[16]; // Null terminated name
|
||||
u32 flash_base; // Address within FLASH of image
|
||||
@@ -73,6 +75,7 @@ static int parse_redboot_partitions(stru
|
||||
const struct mtd_partition **pparts,
|
||||
struct mtd_part_parser_data *data)
|
||||
{
|
||||
+ unsigned long max_offset = 0;
|
||||
int nrparts = 0;
|
||||
struct fis_image_desc *buf;
|
||||
struct mtd_partition *parts;
|
||||
@@ -239,14 +242,15 @@ nogood:
|
||||
}
|
||||
}
|
||||
#endif
|
||||
- parts = kzalloc(sizeof(*parts) * nrparts + nulllen + namelen, GFP_KERNEL);
|
||||
+ parts = kzalloc(sizeof(*parts) * (nrparts + 1) + nulllen + namelen +
|
||||
+ sizeof(BOARD_CONFIG_PART), GFP_KERNEL);
|
||||
|
||||
if (!parts) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
- nullname = (char *)&parts[nrparts];
|
||||
+ nullname = (char *)&parts[nrparts + 1];
|
||||
#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
|
||||
if (nulllen > 0)
|
||||
strcpy(nullname, nullstring);
|
||||
@@ -264,6 +268,8 @@ nogood:
|
||||
}
|
||||
#endif
|
||||
for ( ; i < nrparts; i++) {
|
||||
+ if (max_offset < buf[i].flash_base + buf[i].size)
|
||||
+ max_offset = buf[i].flash_base + buf[i].size;
|
||||
parts[i].size = fl->img->size;
|
||||
parts[i].offset = fl->img->flash_base;
|
||||
parts[i].name = names;
|
||||
@@ -297,6 +303,13 @@ nogood:
|
||||
fl = fl->next;
|
||||
kfree(tmp_fl);
|
||||
}
|
||||
+ if (master->size - max_offset >= master->erasesize) {
|
||||
+ parts[nrparts].size = master->size - max_offset;
|
||||
+ parts[nrparts].offset = max_offset;
|
||||
+ parts[nrparts].name = names;
|
||||
+ strcpy(names, BOARD_CONFIG_PART);
|
||||
+ nrparts++;
|
||||
+ }
|
||||
ret = nrparts;
|
||||
*pparts = parts;
|
||||
out:
|
||||
44
ath25/patches-5.15/141-redboot_partition_scan.patch
Normal file
44
ath25/patches-5.15/141-redboot_partition_scan.patch
Normal file
@ -0,0 +1,44 @@
|
||||
--- a/drivers/mtd/parsers/redboot.c
|
||||
+++ b/drivers/mtd/parsers/redboot.c
|
||||
@@ -94,12 +94,18 @@ static int parse_redboot_partitions(stru
|
||||
|
||||
parse_redboot_of(master);
|
||||
|
||||
+ buf = vmalloc(master->erasesize);
|
||||
+ if (!buf)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+restart:
|
||||
if (directory < 0) {
|
||||
offset = master->size + directory * master->erasesize;
|
||||
while (mtd_block_isbad(master, offset)) {
|
||||
if (!offset) {
|
||||
nogood:
|
||||
pr_notice("Failed to find a non-bad block to check for RedBoot partition table\n");
|
||||
+ vfree(buf);
|
||||
return -EIO;
|
||||
}
|
||||
offset -= master->erasesize;
|
||||
@@ -112,10 +118,6 @@ nogood:
|
||||
goto nogood;
|
||||
}
|
||||
}
|
||||
- buf = vmalloc(master->erasesize);
|
||||
-
|
||||
- if (!buf)
|
||||
- return -ENOMEM;
|
||||
|
||||
pr_notice("Searching for RedBoot partition table in %s at offset 0x%lx\n",
|
||||
master->name, offset);
|
||||
@@ -187,6 +189,11 @@ nogood:
|
||||
}
|
||||
if (i == numslots) {
|
||||
/* Didn't find it */
|
||||
+ if (offset + master->erasesize < master->size) {
|
||||
+ /* not at the end of the flash yet, maybe next block */
|
||||
+ directory++;
|
||||
+ goto restart;
|
||||
+ }
|
||||
pr_notice("No RedBoot partition table detected in %s\n",
|
||||
master->name);
|
||||
ret = 0;
|
||||
83
ath25/patches-5.15/142-redboot_various_erase_size_fix.patch
Normal file
83
ath25/patches-5.15/142-redboot_various_erase_size_fix.patch
Normal file
@ -0,0 +1,83 @@
|
||||
--- a/drivers/mtd/parsers/redboot.c
|
||||
+++ b/drivers/mtd/parsers/redboot.c
|
||||
@@ -71,6 +71,22 @@ static void parse_redboot_of(struct mtd_
|
||||
directory = dirblock;
|
||||
}
|
||||
|
||||
+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset)
|
||||
+{
|
||||
+ struct mtd_erase_region_info *regions = mtd->eraseregions;
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < mtd->numeraseregions; i++) {
|
||||
+ if (regions[i].offset +
|
||||
+ regions[i].numblocks * regions[i].erasesize <= offset)
|
||||
+ continue;
|
||||
+
|
||||
+ return regions[i].erasesize;
|
||||
+ }
|
||||
+
|
||||
+ return mtd->erasesize;
|
||||
+}
|
||||
+
|
||||
static int parse_redboot_partitions(struct mtd_info *master,
|
||||
const struct mtd_partition **pparts,
|
||||
struct mtd_part_parser_data *data)
|
||||
@@ -87,6 +103,7 @@ static int parse_redboot_partitions(stru
|
||||
int namelen = 0;
|
||||
int nulllen = 0;
|
||||
int numslots;
|
||||
+ int first_slot;
|
||||
unsigned long offset;
|
||||
#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
|
||||
static char nullstring[] = "unallocated";
|
||||
@@ -134,7 +151,9 @@ nogood:
|
||||
}
|
||||
|
||||
numslots = (master->erasesize / sizeof(struct fis_image_desc));
|
||||
- for (i = 0; i < numslots; i++) {
|
||||
+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) /
|
||||
+ sizeof(struct fis_image_desc);
|
||||
+ for (i = first_slot; i < first_slot + numslots; i++) {
|
||||
if (!memcmp(buf[i].name, "FIS directory", 14)) {
|
||||
/* This is apparently the FIS directory entry for the
|
||||
* FIS directory itself. The FIS directory size is
|
||||
@@ -200,7 +219,10 @@ nogood:
|
||||
goto out;
|
||||
}
|
||||
|
||||
- for (i = 0; i < numslots; i++) {
|
||||
+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) /
|
||||
+ sizeof(struct fis_image_desc);
|
||||
+
|
||||
+ for (i = first_slot; i < first_slot + numslots; i++) {
|
||||
struct fis_list *new_fl, **prev;
|
||||
|
||||
if (buf[i].name[0] == 0xff) {
|
||||
@@ -275,12 +297,13 @@ nogood:
|
||||
}
|
||||
#endif
|
||||
for ( ; i < nrparts; i++) {
|
||||
- if (max_offset < buf[i].flash_base + buf[i].size)
|
||||
- max_offset = buf[i].flash_base + buf[i].size;
|
||||
parts[i].size = fl->img->size;
|
||||
parts[i].offset = fl->img->flash_base;
|
||||
parts[i].name = names;
|
||||
|
||||
+ if (max_offset < parts[i].offset + parts[i].size)
|
||||
+ max_offset = parts[i].offset + parts[i].size;
|
||||
+
|
||||
strcpy(names, fl->img->name);
|
||||
#ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY
|
||||
if (!memcmp(names, "RedBoot", 8) ||
|
||||
@@ -310,7 +333,9 @@ nogood:
|
||||
fl = fl->next;
|
||||
kfree(tmp_fl);
|
||||
}
|
||||
- if (master->size - max_offset >= master->erasesize) {
|
||||
+
|
||||
+ if (master->size - max_offset >=
|
||||
+ mtd_get_offset_erasesize(master, max_offset)) {
|
||||
parts[nrparts].size = master->size - max_offset;
|
||||
parts[nrparts].offset = max_offset;
|
||||
parts[nrparts].name = names;
|
||||
71
ath25/patches-5.15/210-reset_button.patch
Normal file
71
ath25/patches-5.15/210-reset_button.patch
Normal file
@ -0,0 +1,71 @@
|
||||
--- a/arch/mips/ath25/Makefile
|
||||
+++ b/arch/mips/ath25/Makefile
|
||||
@@ -8,7 +8,7 @@
|
||||
# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
|
||||
#
|
||||
|
||||
-obj-y += board.o prom.o devices.o
|
||||
+obj-y += board.o prom.o devices.o reset.o
|
||||
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/mips/ath25/reset.c
|
||||
@@ -0,0 +1,57 @@
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/gpio_keys.h>
|
||||
+#include <linux/input.h>
|
||||
+#include <ath25_platform.h>
|
||||
+#include "devices.h"
|
||||
+
|
||||
+static int __init
|
||||
+ar231x_init_reset(void)
|
||||
+{
|
||||
+ struct platform_device *pdev;
|
||||
+ struct gpio_keys_platform_data pdata;
|
||||
+ struct gpio_keys_button *p;
|
||||
+ int err;
|
||||
+
|
||||
+ if (ath25_board.config->reset_config_gpio == 0xffff)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ p = kzalloc(sizeof(*p), GFP_KERNEL);
|
||||
+ if (!p)
|
||||
+ goto err;
|
||||
+
|
||||
+ p->desc = "reset";
|
||||
+ p->type = EV_KEY;
|
||||
+ p->code = KEY_RESTART;
|
||||
+ p->debounce_interval = 60;
|
||||
+ p->gpio = ath25_board.config->reset_config_gpio;
|
||||
+
|
||||
+ memset(&pdata, 0, sizeof(pdata));
|
||||
+ pdata.poll_interval = 20;
|
||||
+ pdata.buttons = p;
|
||||
+ pdata.nbuttons = 1;
|
||||
+
|
||||
+ pdev = platform_device_alloc("gpio-keys-polled", 0);
|
||||
+ if (!pdev)
|
||||
+ goto err_free;
|
||||
+
|
||||
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
|
||||
+ if (err)
|
||||
+ goto err_put_pdev;
|
||||
+
|
||||
+ err = platform_device_add(pdev);
|
||||
+ if (err)
|
||||
+ goto err_put_pdev;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+err_put_pdev:
|
||||
+ platform_device_put(pdev);
|
||||
+err_free:
|
||||
+ kfree(p);
|
||||
+err:
|
||||
+ return -ENOMEM;
|
||||
+}
|
||||
+
|
||||
+device_initcall(ar231x_init_reset);
|
||||
111
ath25/patches-5.15/220-enet_micrel_workaround.patch
Normal file
111
ath25/patches-5.15/220-enet_micrel_workaround.patch
Normal file
@ -0,0 +1,111 @@
|
||||
--- a/drivers/net/ethernet/atheros/ar231x/ar231x.c
|
||||
+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
|
||||
@@ -133,6 +133,7 @@ static int ar231x_mdiobus_write(struct m
|
||||
static int ar231x_mdiobus_reset(struct mii_bus *bus);
|
||||
static int ar231x_mdiobus_probe(struct net_device *dev);
|
||||
static void ar231x_adjust_link(struct net_device *dev);
|
||||
+static bool no_phy;
|
||||
|
||||
#ifndef ERR
|
||||
#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
|
||||
@@ -164,6 +165,32 @@ static const struct net_device_ops ar231
|
||||
#endif
|
||||
};
|
||||
|
||||
+static int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id)
|
||||
+{
|
||||
+ int phy_reg;
|
||||
+
|
||||
+ /**
|
||||
+ * Grab the bits from PHYIR1, and put them
|
||||
+ * in the upper half.
|
||||
+ */
|
||||
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
|
||||
+
|
||||
+ if (phy_reg < 0)
|
||||
+ return -EIO;
|
||||
+
|
||||
+ *phy_id = (phy_reg & 0xffff) << 16;
|
||||
+
|
||||
+ /* Grab the bits from PHYIR2, and put them in the lower half */
|
||||
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
|
||||
+
|
||||
+ if (phy_reg < 0)
|
||||
+ return -EIO;
|
||||
+
|
||||
+ *phy_id |= (phy_reg & 0xffff);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int ar231x_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *dev;
|
||||
@@ -271,6 +298,24 @@ static int ar231x_probe(struct platform_
|
||||
|
||||
mdiobus_register(sp->mii_bus);
|
||||
|
||||
+ /**
|
||||
+ * Workaround for Micrel switch, which is only available on
|
||||
+ * one PHY and cannot be configured through MDIO.
|
||||
+ */
|
||||
+ if (!no_phy) {
|
||||
+ u32 phy_id = 0;
|
||||
+
|
||||
+ get_phy_id(sp->mii_bus, 1, &phy_id);
|
||||
+ if (phy_id == 0x00221450)
|
||||
+ no_phy = true;
|
||||
+ }
|
||||
+ if (no_phy) {
|
||||
+ sp->link = 1;
|
||||
+ netif_carrier_on(dev);
|
||||
+ return 0;
|
||||
+ }
|
||||
+ no_phy = true;
|
||||
+
|
||||
if (ar231x_mdiobus_probe(dev) != 0) {
|
||||
printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
|
||||
rx_tasklet_cleanup(dev);
|
||||
@@ -324,8 +369,10 @@ static int ar231x_remove(struct platform
|
||||
rx_tasklet_cleanup(dev);
|
||||
ar231x_init_cleanup(dev);
|
||||
unregister_netdev(dev);
|
||||
- mdiobus_unregister(sp->mii_bus);
|
||||
- mdiobus_free(sp->mii_bus);
|
||||
+ if (sp->mii_bus) {
|
||||
+ mdiobus_unregister(sp->mii_bus);
|
||||
+ mdiobus_free(sp->mii_bus);
|
||||
+ }
|
||||
kfree(dev);
|
||||
return 0;
|
||||
}
|
||||
@@ -868,7 +915,8 @@ static int ar231x_open(struct net_device
|
||||
|
||||
sp->eth_regs->mac_control |= MAC_CONTROL_RE;
|
||||
|
||||
- phy_start(sp->phy_dev);
|
||||
+ if (sp->phy_dev)
|
||||
+ phy_start(sp->phy_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -949,7 +997,8 @@ static int ar231x_close(struct net_devic
|
||||
|
||||
#endif
|
||||
|
||||
- phy_stop(sp->phy_dev);
|
||||
+ if (sp->phy_dev)
|
||||
+ phy_stop(sp->phy_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -993,6 +1042,9 @@ static int ar231x_ioctl(struct net_devic
|
||||
{
|
||||
struct ar231x_private *sp = netdev_priv(dev);
|
||||
|
||||
+ if (!sp->phy_dev)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
switch (cmd) {
|
||||
case SIOCGMIIPHY:
|
||||
case SIOCGMIIREG:
|
||||
116
ath25/patches-5.15/330-board_leds.patch
Normal file
116
ath25/patches-5.15/330-board_leds.patch
Normal file
@ -0,0 +1,116 @@
|
||||
--- a/arch/mips/ath25/ar2315.c
|
||||
+++ b/arch/mips/ath25/ar2315.c
|
||||
@@ -24,6 +24,7 @@
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/gpio.h>
|
||||
+#include <linux/leds.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
@@ -258,6 +259,50 @@ static struct platform_device ar2315_spi
|
||||
.num_resources = ARRAY_SIZE(ar2315_spiflash_res)
|
||||
};
|
||||
|
||||
+#ifdef CONFIG_LEDS_GPIO
|
||||
+static struct gpio_led ar2315_leds[6];
|
||||
+static struct gpio_led_platform_data ar2315_led_data = {
|
||||
+ .leds = (void *)ar2315_leds,
|
||||
+};
|
||||
+
|
||||
+static struct platform_device ar2315_gpio_leds = {
|
||||
+ .name = "leds-gpio",
|
||||
+ .id = -1,
|
||||
+ .dev = {
|
||||
+ .platform_data = (void *)&ar2315_led_data,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
+static void __init ar2315_init_gpio_leds(void)
|
||||
+{
|
||||
+ static char led_names[6][6];
|
||||
+ int i, led = 0;
|
||||
+
|
||||
+ ar2315_led_data.num_leds = 0;
|
||||
+ for (i = 1; i < 8; i++) {
|
||||
+ if ((i == AR2315_RESET_GPIO) ||
|
||||
+ (i == ath25_board.config->reset_config_gpio))
|
||||
+ continue;
|
||||
+
|
||||
+ if (i == ath25_board.config->sys_led_gpio)
|
||||
+ strcpy(led_names[led], "wlan");
|
||||
+ else
|
||||
+ sprintf(led_names[led], "gpio%d", i);
|
||||
+
|
||||
+ ar2315_leds[led].name = led_names[led];
|
||||
+ ar2315_leds[led].gpio = i;
|
||||
+ ar2315_leds[led].active_low = 0;
|
||||
+ led++;
|
||||
+ }
|
||||
+ ar2315_led_data.num_leds = led;
|
||||
+ platform_device_register(&ar2315_gpio_leds);
|
||||
+}
|
||||
+#else
|
||||
+static inline void ar2315_init_gpio_leds(void)
|
||||
+{
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
void __init ar2315_init_devices(void)
|
||||
{
|
||||
/* Find board configuration */
|
||||
@@ -268,6 +313,8 @@ void __init ar2315_init_devices(void)
|
||||
ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
|
||||
platform_device_register(&ar2315_gpio);
|
||||
|
||||
+ ar2315_init_gpio_leds();
|
||||
+
|
||||
ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
|
||||
AR2315_MISC_IRQ_WATCHDOG);
|
||||
ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
|
||||
--- a/arch/mips/ath25/ar5312.c
|
||||
+++ b/arch/mips/ath25/ar5312.c
|
||||
@@ -24,6 +24,7 @@
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/gpio.h>
|
||||
+#include <linux/leds.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
@@ -228,6 +229,23 @@ static struct platform_device ar5312_gpi
|
||||
.num_resources = ARRAY_SIZE(ar5312_gpio_res),
|
||||
};
|
||||
|
||||
+#ifdef CONFIG_LEDS_GPIO
|
||||
+static struct gpio_led ar5312_leds[] = {
|
||||
+ { .name = "wlan", .gpio = 0, .active_low = 1, },
|
||||
+};
|
||||
+
|
||||
+static const struct gpio_led_platform_data ar5312_led_data = {
|
||||
+ .num_leds = ARRAY_SIZE(ar5312_leds),
|
||||
+ .leds = (void *)ar5312_leds,
|
||||
+};
|
||||
+
|
||||
+static struct platform_device ar5312_gpio_leds = {
|
||||
+ .name = "leds-gpio",
|
||||
+ .id = -1,
|
||||
+ .dev.platform_data = (void *)&ar5312_led_data,
|
||||
+};
|
||||
+#endif
|
||||
+
|
||||
static void __init ar5312_flash_init(void)
|
||||
{
|
||||
void __iomem *flashctl_base;
|
||||
@@ -298,6 +316,11 @@ void __init ar5312_init_devices(void)
|
||||
|
||||
platform_device_register(&ar5312_gpio);
|
||||
|
||||
+#ifdef CONFIG_LEDS_GPIO
|
||||
+ ar5312_leds[0].gpio = config->sys_led_gpio;
|
||||
+ platform_device_register(&ar5312_gpio_leds);
|
||||
+#endif
|
||||
+
|
||||
/* Fix up MAC addresses if necessary */
|
||||
if (is_broadcast_ether_addr(config->enet0_mac))
|
||||
ether_addr_copy(config->enet0_mac, config->enet1_mac);
|
||||
23
ath25/patches-5.15/700-swconfig_mvswitch.patch
Normal file
23
ath25/patches-5.15/700-swconfig_mvswitch.patch
Normal file
@ -0,0 +1,23 @@
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -96,6 +96,10 @@ config IP17XX_PHY
|
||||
tristate "Driver for IC+ IP17xx switches"
|
||||
select SWCONFIG
|
||||
|
||||
+config MVSWITCH_PHY
|
||||
+ tristate "Driver for Marvell 88E6060 switches"
|
||||
+ select ETHERNET_PACKET_MANGLE
|
||||
+
|
||||
config PSB6970_PHY
|
||||
tristate "Lantiq XWAY Tantos (PSB6970) Ethernet switch"
|
||||
select SWCONFIG
|
||||
--- a/drivers/net/phy/Makefile
|
||||
+++ b/drivers/net/phy/Makefile
|
||||
@@ -31,6 +31,7 @@ ar8xxx-y += ar8216.o
|
||||
ar8xxx-y += ar8327.o
|
||||
obj-$(CONFIG_SWCONFIG_B53) += b53/
|
||||
obj-$(CONFIG_IP17XX_PHY) += ip17xx.o
|
||||
+obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o
|
||||
obj-$(CONFIG_PSB6970_PHY) += psb6970.o
|
||||
obj-$(CONFIG_RTL8306_PHY) += rtl8306.o
|
||||
obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o
|
||||
13
ath25/profiles/00-default.mk
Normal file
13
ath25/profiles/00-default.mk
Normal file
@ -0,0 +1,13 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Copyright (C) 2011 OpenWrt.org
|
||||
|
||||
define Profile/Default
|
||||
NAME:=Default Profile
|
||||
PRIORITY:=1
|
||||
endef
|
||||
|
||||
define Profile/Default/Description
|
||||
Default package set compatible with most boards.
|
||||
endef
|
||||
$(eval $(call Profile,Default))
|
||||
Loading…
Reference in New Issue
Block a user